verilog: significant block scoping improvements

[yosys.git] / techlibs / common / mul2dsp.v

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index 4cabb4453e91c7714fc37e620b72ddb4430965e2..f22f47b4a54de68a6e41e0ca8c28d0f670461c0a 100644 (file)
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -57,8 +57,11 @@ module _80_mul (A, B, Y);
        parameter B_WIDTH = 1;\r
        parameter Y_WIDTH = 1;\r
 \r
+       (* force_downto *)\r
        input [A_WIDTH-1:0] A;\r
+       (* force_downto *)\r
        input [B_WIDTH-1:0] B;\r
+       (* force_downto *)\r
        output [Y_WIDTH-1:0] Y;\r
 \r
        parameter _TECHMAP_CELLTYPE_ = "";\r
@@ -118,14 +121,20 @@ module _80_mul (A, B, Y);
                        localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL);\r
                        localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);\r
                        localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;\r
-                       if (A_SIGNED && B_SIGNED) begin\r
+                       if (A_SIGNED && B_SIGNED) begin : blk\r
+                               (* force_downto *)\r
                                wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];\r
+                               (* force_downto *)\r
                                wire signed [last_Y_WIDTH-1:0] last_partial;\r
+                               (* force_downto *)\r
                                wire signed [Y_WIDTH-1:0] partial_sum [n:0];\r
                        end\r
-                       else begin\r
+                       else begin : blk\r
+                               (* force_downto *)\r
                                wire [partial_Y_WIDTH-1:0] partial [n-1:0];\r
+                               (* force_downto *)\r
                                wire [last_Y_WIDTH-1:0] last_partial;\r
+                               (* force_downto *)\r
                                wire [Y_WIDTH-1:0] partial_sum [n:0];\r
                        end\r
 \r
@@ -139,15 +148,15 @@ module _80_mul (A, B, Y);
                                ) mul (\r
                                        .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}),\r
                                        .B(B),\r
-                                       .Y(partial[i])\r
+                                       .Y(blk.partial[i])\r
                                );\r
                                // TODO: Currently a 'cascade' approach to summing the partial\r
                                //       products is taken here, but a more efficient 'binary\r
                                //       reduction' approach also exists...\r
                                if (i == 0)\r
-                                       assign partial_sum[i] = partial[i];\r
+                                       assign blk.partial_sum[i] = blk.partial[i];\r
                                else\r
-                                       assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1];\r
+                                       assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];\r
                        end\r
 \r
                        \$__mul #(\r
@@ -159,24 +168,30 @@ module _80_mul (A, B, Y);
                        ) sliceA.last (\r
                                .A(A[A_WIDTH-1 -: last_A_WIDTH]),\r
                                .B(B),\r
-                               .Y(last_partial)\r
+                               .Y(blk.last_partial)\r
                        );\r
-                       assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1];\r
-                       assign Y = partial_sum[n];\r
+                       assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];\r
+                       assign Y = blk.partial_sum[n];\r
                end\r
                else if (B_WIDTH > `DSP_B_MAXWIDTH) begin\r
                        localparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);\r
                        localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL);\r
                        localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);\r
                        localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;\r
-                       if (A_SIGNED && B_SIGNED) begin\r
+                       if (A_SIGNED && B_SIGNED) begin : blk\r
+                               (* force_downto *)\r
                                wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];\r
+                               (* force_downto *)\r
                                wire signed [last_Y_WIDTH-1:0] last_partial;\r
+                               (* force_downto *)\r
                                wire signed [Y_WIDTH-1:0] partial_sum [n:0];\r
                        end\r
-                       else begin\r
+                       else begin : blk\r
+                               (* force_downto *)\r
                                wire [partial_Y_WIDTH-1:0] partial [n-1:0];\r
+                               (* force_downto *)\r
                                wire [last_Y_WIDTH-1:0] last_partial;\r
+                               (* force_downto *)\r
                                wire [Y_WIDTH-1:0] partial_sum [n:0];\r
                        end\r
 \r
@@ -190,15 +205,15 @@ module _80_mul (A, B, Y);
                                ) mul (\r
                                        .A(A),\r
                                        .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}),\r
-                                       .Y(partial[i])\r
+                                       .Y(blk.partial[i])\r
                                );\r
                                // TODO: Currently a 'cascade' approach to summing the partial\r
                                //       products is taken here, but a more efficient 'binary\r
                                //       reduction' approach also exists...\r
                                if (i == 0)\r
-                                       assign partial_sum[i] = partial[i];\r
+                                       assign blk.partial_sum[i] = blk.partial[i];\r
                                else\r
-                                       assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1];\r
+                                       assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];\r
                        end\r
 \r
                        \$__mul #(\r
@@ -210,20 +225,24 @@ module _80_mul (A, B, Y);
                        ) mul_sliceB_last (\r
                                .A(A),\r
                                .B(B[B_WIDTH-1 -: last_B_WIDTH]),\r
-                               .Y(last_partial)\r
+                               .Y(blk.last_partial)\r
                        );\r
-                       assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1];\r
-                       assign Y = partial_sum[n];\r
+                       assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];\r
+                       assign Y = blk.partial_sum[n];\r
                end\r
                else begin\r
-                       if (A_SIGNED)\r
+                       if (A_SIGNED) begin : blkA\r
                                wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);\r
-                       else\r
+                       end\r
+                       else begin : blkA\r
                                wire [`DSP_A_MAXWIDTH-1:0] Aext = A;\r
-                       if (B_SIGNED)\r
+                       end\r
+                       if (B_SIGNED) begin : blkB\r
                                wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);\r
-                       else\r
+                       end\r
+                       else begin : blkB\r
                                wire [`DSP_B_MAXWIDTH-1:0] Bext = B;\r
+                       end\r
 \r
                        `DSP_NAME #(\r
                                .A_SIGNED(A_SIGNED),\r
@@ -232,8 +251,8 @@ module _80_mul (A, B, Y);
                                .B_WIDTH(`DSP_B_MAXWIDTH),\r
                                .Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),\r
                        ) _TECHMAP_REPLACE_ (\r
-                               .A(Aext),\r
-                               .B(Bext),\r
+                               .A(blkA.Aext),\r
+                               .B(blkB.Bext),\r
                                .Y(Y)\r
                        );\r
                end\r
@@ -249,8 +268,11 @@ module _90_soft_mul (A, B, Y);
        parameter B_WIDTH = 1;\r
        parameter Y_WIDTH = 1;\r
 \r
+       (* force_downto *)\r
        input [A_WIDTH-1:0] A;\r
+       (* force_downto *)\r
        input [B_WIDTH-1:0] B;\r
+       (* force_downto *)\r
        output [Y_WIDTH-1:0] Y;\r
 \r
        // Indirection necessary since mapping\r