Added $assert cell

[yosys.git] / techlibs / common / simlib.v

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 0e041e12eeab5802b1cbf136d47eb5ae843088ce..8f354a63d19edb0d8b018756dd7ccbaac234f053 100644 (file)
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -733,6 +733,21 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$assert (A, EN);
+
+input A, EN;
+
+always @* begin
+       if (A !== 1'b1 && EN === 1'b1) begin
+               $display("Assertation failed!");
+               $finish;
+       end
+end
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$sr (SET, CLR, Q);
 
 parameter WIDTH = 0;