* The internal logic cell technology mapper.
*
* This verilog library contains the mapping of internal cells (e.g. $not with
- * variable bit width) to the internal logic cells (such as the single bit $_INV_
+ * variable bit width) to the internal logic cells (such as the single bit $_NOT_
* gate). Usually this logic network is then mapped to the actual technology
* using e.g. the "abc" pass.
*
// Use simplemap for trivial cell types
// --------------------------------------------------------
-(* techmap_simplemap *)
-(* techmap_celltype = "$pos $bu0" *)
-module simplemap_buffers;
-endmodule
-
(* techmap_simplemap *)
(* techmap_celltype = "$not $and $or $xor $xnor" *)
module simplemap_bool_ops;
endmodule
(* techmap_simplemap *)
-(* techmap_celltype = "$slice $concat $mux" *)
+(* techmap_celltype = "$pos $slice $concat $mux" *)
module simplemap_various;
endmodule
// ALU Infrastructure
// --------------------------------------------------------
-module \$__alu_ripple (A, B, CI, Y, CO, CS);
+module \$fa (A, B, C, X, Y);
parameter WIDTH = 1;
- input [WIDTH-1:0] A, B;
- output [WIDTH-1:0] Y;
+ input [WIDTH-1:0] A, B, C;
+ output [WIDTH-1:0] X, Y;
- input CI;
- output CO, CS;
+ wire [WIDTH-1:0] t1, t2, t3;
- wire [WIDTH:0] carry;
- assign carry[0] = CI;
- assign CO = carry[WIDTH];
- assign CS = carry[WIDTH-1];
-
- genvar i;
- generate
- for (i = 0; i < WIDTH; i = i + 1)
- begin:V
- // {x, y} = a + b + c
- wire a, b, c, x, y;
- wire t1, t2, t3;
-
- \$_AND_ gate1 ( .A(a), .B(b), .Y(t1) );
- \$_XOR_ gate2 ( .A(a), .B(b), .Y(t2) );
- \$_AND_ gate3 ( .A(t2), .B(c), .Y(t3) );
- \$_XOR_ gate4 ( .A(t2), .B(c), .Y(y) );
- \$_OR_ gate5 ( .A(t1), .B(t3), .Y(x) );
-
- assign a = A[i], b = B[i], c = carry[i];
- assign carry[i+1] = x, Y[i] = y;
- end
- endgenerate
+ assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
+ assign Y = t1 ^ C, X = t2 | t3;
endmodule
-module \$__lcu (P, G, CI, CO, PG, GG);
- parameter WIDTH = 1;
+module \$lcu (P, G, CI, CO);
+ parameter WIDTH = 2;
input [WIDTH-1:0] P, G;
input CI;
- output [WIDTH:0] CO;
- output PG, GG;
-
- assign CO[0] = CI;
- assign PG = 'bx, GG = 'bx;
-
- genvar i;
- generate
- // TBD: Actually implement a LCU topology
- for (i = 0; i < WIDTH; i = i + 1)
- assign CO[i+1] = G[i] | (P[i] & CO[i]);
- endgenerate
-endmodule
-
-module \$__alu_lookahead (A, B, CI, Y, CO, CS);
- parameter WIDTH = 1;
+ output [WIDTH-1:0] CO;
- input [WIDTH-1:0] A, B;
- output [WIDTH-1:0] Y;
+ integer i, j;
+ reg [WIDTH-1:0] p, g;
- input CI;
- output CO, CS;
+ wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
- wire [WIDTH-1:0] P, G;
- wire [WIDTH:0] C;
+ always @* begin
+ p = P;
+ g = G;
- assign CO = C[WIDTH];
- assign CS = C[WIDTH-1];
+ // in almost all cases CI will be constant zero
+ g[0] = g[0] | (p[0] & CI);
- genvar i;
- generate
- for (i = 0; i < WIDTH; i = i + 1)
- begin:V
- wire a, b, c, p, g, y;
+ // [[CITE]] Brent Kung Adder
+ // R. P. Brent and H. T. Kung, “A Regular Layout for Parallel Adders”,
+ // IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982
- \$_AND_ gate1 ( .A(a), .B(b), .Y(g) );
- \$_XOR_ gate2 ( .A(a), .B(b), .Y(p) );
- \$_XOR_ gate3 ( .A(p), .B(c), .Y(y) );
+ // Main tree
+ for (i = 1; i <= $clog2(WIDTH); i = i+1) begin
+ for (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin
+ g[j] = g[j] | p[j] & g[j - 2**(i-1)];
+ p[j] = p[j] & p[j - 2**(i-1)];
+ end
+ end
- assign a = A[i], b = B[i], c = C[i];
- assign P[i] = p, G[i] = g, Y[i] = y;
+ // Inverse tree
+ for (i = $clog2(WIDTH); i > 0; i = i-1) begin
+ for (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin
+ g[j] = g[j] | p[j] & g[j - 2**(i-1)];
+ p[j] = p[j] & p[j - 2**(i-1)];
+ end
end
- endgenerate
+ end
- \$__lcu #(.WIDTH(WIDTH)) lcu (.P(P), .G(G), .CI(CI), .CO(C));
+ assign CO = g;
endmodule
-module \$__alu (A, B, CI, S, Y, CO, CS);
+module \$alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
- output [Y_WIDTH-1:0] Y;
+ output [Y_WIDTH-1:0] X, Y;
- // carry in, sub, carry out, carry sign
- input CI, S;
- output CO, CS;
+ input CI, BI;
+ output [Y_WIDTH-1:0] CO;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
-`ifdef ALU_RIPPLE
- \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(S ? ~B_buf : B_buf), .CI(CI), .Y(Y), .CO(CO), .CS(CS));
-`else
- if (Y_WIDTH <= 4) begin
- \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(S ? ~B_buf : B_buf), .CI(CI), .Y(Y), .CO(CO), .CS(CS));
- end else begin
- \$__alu_lookahead #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(S ? ~B_buf : B_buf), .CI(CI), .Y(Y), .CO(CO), .CS(CS));
- end
-`endif
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+
+ \$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));
+
+ assign X = AA ^ BB;
+ assign Y = X ^ {CO, CI};
endmodule
-`define ALU_COMMONS(_width, _ci, _s) """
+
+// --------------------------------------------------------
+// ALU Cell Types: Compare, Add, Subtract
+// --------------------------------------------------------
+
+`define ALU_COMMONS(_width, _sub) """
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
- wire alu_co, alu_cs;
- wire [WIDTH-1:0] alu_y;
+ wire [WIDTH-1:0] alu_x, alu_y, alu_co;
+ wire [WIDTH:0] carry = {alu_co, |_sub};
- \$__alu #(
+ \$alu #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH),
) alu (
.A(A),
.B(B),
- .CI(_ci),
- .S(_s),
+ .CI(|_sub),
+ .BI(|_sub),
+ .X(alu_x),
.Y(alu_y),
- .CO(alu_co),
- .CS(alu_cs)
+ .CO(alu_co)
);
wire cf, of, zf, sf;
- assign cf = !alu_co;
- assign of = alu_co ^ alu_cs;
- assign zf = ~|alu_y;
+ assign cf = !carry[WIDTH];
+ assign of = carry[WIDTH] ^ carry[WIDTH-1];
assign sf = alu_y[WIDTH-1];
"""
-
-// --------------------------------------------------------
-// Compare cells
-// --------------------------------------------------------
-
module \$lt (A, B, Y);
- wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt_const -mux_undef -mux_bool -fine;;;";
- `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
+ wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
+ `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1)
assign Y = A_SIGNED && B_SIGNED ? of != sf : cf;
endmodule
module \$le (A, B, Y);
- wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt_const -mux_undef -mux_bool -fine;;;";
- `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
- assign Y = zf || (A_SIGNED && B_SIGNED ? of != sf : cf);
+ wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
+ `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1)
+ assign Y = &alu_x || (A_SIGNED && B_SIGNED ? of != sf : cf);
endmodule
-
-// --------------------------------------------------------
-// Add and Subtract
-// --------------------------------------------------------
-
module \$add (A, B, Y);
- wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt_const -mux_undef -mux_bool -fine;;;";
- `ALU_COMMONS(Y_WIDTH, 0, 0)
+ wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
+ `ALU_COMMONS(Y_WIDTH, 0)
assign Y = alu_y;
endmodule
module \$sub (A, B, Y);
- wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt_const -mux_undef -mux_bool -fine;;;";
- `ALU_COMMONS(Y_WIDTH, 1, 1)
+ wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
+ `ALU_COMMONS(Y_WIDTH, 1)
assign Y = alu_y;
endmodule
// Multiply
// --------------------------------------------------------
-module \$__arraymul (A, B, Y);
- parameter WIDTH = 8;
- input [WIDTH-1:0] A, B;
- output [WIDTH-1:0] Y;
-
- wire [WIDTH*WIDTH-1:0] partials;
-
- genvar i;
- assign partials[WIDTH-1 : 0] = A[0] ? B : 0;
- generate for (i = 1; i < WIDTH; i = i+1) begin:gen
- assign partials[WIDTH*(i+1)-1 : WIDTH*i] = (A[i] ? B << i : 0) + partials[WIDTH*i-1 : WIDTH*(i-1)];
- end endgenerate
-
- assign Y = partials[WIDTH*WIDTH-1 : WIDTH*(WIDTH-1)];
+(* techmap_maccmap *)
+module \$macc ;
endmodule
module \$mul (A, B, Y);
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
- wire [Y_WIDTH-1:0] A_buf, B_buf;
- \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
- \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt -purge";
- \$__arraymul #(
- .WIDTH(Y_WIDTH)
- ) arraymul (
- .A(A_buf),
- .B(B_buf),
+ localparam [ 3:0] CONFIG_WIDTH_BITS = 15;
+ localparam [ 0:0] CONFIG_IS_SIGNED = A_SIGNED && B_SIGNED;
+ localparam [ 0:0] CONFIG_DO_SUBTRACT = 0;
+ localparam [14:0] CONFIG_A_WIDTH = A_WIDTH;
+ localparam [14:0] CONFIG_B_WIDTH = B_WIDTH;
+
+ \$macc #(
+ .CONFIG({CONFIG_B_WIDTH, CONFIG_A_WIDTH, CONFIG_DO_SUBTRACT, CONFIG_IS_SIGNED, CONFIG_WIDTH_BITS}),
+ .CONFIG_WIDTH(15 + 15 + 2 + 4),
+ .A_WIDTH(B_WIDTH + A_WIDTH),
+ .B_WIDTH(0),
+ .Y_WIDTH(Y_WIDTH)
+ ) _TECHMAP_REPLACE_ (
+ .A({B, A}),
+ .B(),
.Y(Y)
);
endmodule
wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf;
- \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
- \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
assign Y = ~|(A_buf ^ B_buf);
endmodule
wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf;
- \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
- \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
assign Y = |(A_buf ^ B_buf);
endmodule
assign Y = |S ? Y_B : A;
endmodule
-module \$safe_pmux (A, B, S, Y);
- parameter WIDTH = 1;
- parameter S_WIDTH = 1;
- input [WIDTH-1:0] A;
- input [WIDTH*S_WIDTH-1:0] B;
- input [S_WIDTH-1:0] S;
- output [WIDTH-1:0] Y;
+// --------------------------------------------------------
+// LUTs
+// --------------------------------------------------------
- wire [S_WIDTH-1:0] status_found_first;
- wire [S_WIDTH-1:0] status_found_second;
+`ifndef NOLUT
+module \$lut (A, Y);
+ parameter WIDTH = 1;
+ parameter LUT = 0;
- genvar i;
- generate
- for (i = 0; i < S_WIDTH; i = i + 1) begin:GEN1
- wire pre_first;
- if (i > 0) begin:GEN2
- assign pre_first = status_found_first[i-1];
- end:GEN2 else begin:GEN3
- assign pre_first = 0;
- end:GEN3
- assign status_found_first[i] = pre_first | S[i];
- assign status_found_second[i] = pre_first & S[i];
- end:GEN1
- endgenerate
+ input [WIDTH-1:0] A;
+ output Y;
- \$pmux #(
- .WIDTH(WIDTH),
- .S_WIDTH(S_WIDTH)
- ) pmux_cell (
- .A(A),
- .B(B),
- .S(S & {S_WIDTH{~|status_found_second}}),
- .Y(Y)
- );
+ assign Y = LUT[A];
endmodule
+`endif
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