log(" do not use flipflops with CE in output netlist\n");
log("\n");
log(" -nobram\n");
- log(" do not use BRAM cells in output netlist\n");
+ log(" do not use block RAM cells in output netlist\n");
log("\n");
- log(" -nodram\n");
- log(" do not use distributed RAM cells in output netlist\n");
+ log(" -nolutram\n");
+ log(" do not use LUT RAM cells in output netlist\n");
log("\n");
log(" -nowidelut\n");
log(" do not use PFU muxes to implement LUTs larger than LUT4s\n");
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
log(" (this feature is experimental and incomplete)\n");
log("\n");
- log(" -dsp\n");
- log(" map multipliers to MULT18X18D (EXPERIMENTAL)\n");
+ log(" -nodsp\n");
+ log(" do not map multipliers to MULT18X18D\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
}
string top_opt, blif_file, edif_file, json_file;
- bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, abc9, dsp, vpr;
+ bool noccu2, nodffe, nobram, nolutram, nowidelut, flatten, retime, abc2, abc9, nodsp, vpr;
void clear_flags() YS_OVERRIDE
{
noccu2 = false;
nodffe = false;
nobram = false;
- nodram = false;
+ nolutram = false;
nowidelut = false;
flatten = true;
retime = false;
abc2 = false;
vpr = false;
abc9 = false;
- dsp = false;
+ nodsp = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
nobram = true;
continue;
}
- if (args[argidx] == "-nodram") {
- nodram = true;
+ if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
+ nolutram = true;
continue;
}
- if (args[argidx] == "-nowidelut" || args[argidx] == "-nomux") {
+ if (args[argidx] == "-nowidelut" || /*deprecated alias*/ args[argidx] == "-nomux") {
nowidelut = true;
continue;
}
abc9 = true;
continue;
}
- if (args[argidx] == "-dsp") {
- dsp = true;
+ if (args[argidx] == "-nodsp") {
+ nodsp = true;
continue;
}
break;
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
run("opt_expr");
run("opt_clean");
- if (dsp) {
- run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL18X18");
- run("clean");
- run("techmap -map +/ecp5/dsp_map.v");
+ if (!nodsp) {
+ run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18", "(unless -nodsp)");
+ run("clean", "(unless -nodsp)");
+ run("techmap -map +/ecp5/dsp_map.v", "(unless -nodsp)");
+ run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)");
}
run("alumacc");
run("opt");
run("opt_clean");
}
- if (!nobram && check_label("bram", "(skip if -nobram)"))
+ if (!nobram && check_label("map_bram", "(skip if -nobram)"))
{
run("memory_bram -rules +/ecp5/bram.txt");
run("techmap -map +/ecp5/brams_map.v");
}
- if (!nodram && check_label("dram", "(skip if -nodram)"))
+ if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
{
- run("memory_bram -rules +/ecp5/dram.txt");
- run("techmap -map +/ecp5/drams_map.v");
+ run("memory_bram -rules +/ecp5/lutram.txt");
+ run("techmap -map +/ecp5/lutrams_map.v");
}
- if (check_label("fine"))
+ if (check_label("map_ffram"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
+ }
+
+ if (check_label("map_gates"))
+ {
if (noccu2)
run("techmap");
else
run("opt_expr -undriven -mux_undef");
run("simplemap");
run("ecp5_ffinit");
+ run("ecp5_gsr");
+ run("opt_clean");
}
if (check_label("map_luts"))
if (abc2 || help_mode) {
run("abc", " (only if -abc2)");
}
- run("techmap -map +/ecp5/latches_map.v");
+ std::string techmap_args = "-map +/ecp5/latches_map.v";
+ if (abc9)
+ techmap_args += " -map +/ecp5/abc_map.v -max_iter 1";
+ run("techmap " + techmap_args);
+
if (abc9) {
if (nowidelut)
run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
else
run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
+ run("techmap -map +/ecp5/abc_unmap.v");
} else {
if (nowidelut)
run("abc -lut 4 -dress");