* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- * Copyright (C) 2018 Clifford Wolf <dave@ds0.me>
+ * Copyright (C) 2018 David Shah <dave@ds0.me>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
log(" do not use flipflops with CE in output netlist\n");
log("\n");
log(" -nobram\n");
- log(" do not use BRAM cells in output netlist\n");
+ log(" do not use block RAM cells in output netlist\n");
log("\n");
- log(" -nodram\n");
- log(" do not use distributed RAM cells in output netlist\n");
+ log(" -nolutram\n");
+ log(" do not use LUT RAM cells in output netlist\n");
log("\n");
- log(" -nomux\n");
+ log(" -nowidelut\n");
log(" do not use PFU muxes to implement LUTs larger than LUT4s\n");
log("\n");
log(" -abc2\n");
log(" run two passes of 'abc' for slightly improved logic density\n");
log("\n");
+ log(" -abc9\n");
+ log(" use new ABC9 flow (EXPERIMENTAL)\n");
+ log("\n");
log(" -vpr\n");
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
log(" (this feature is experimental and incomplete)\n");
log("\n");
+ log(" -dsp\n");
+ log(" map multipliers to MULT18X18D (EXPERIMENTAL)\n");
+ log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
}
string top_opt, blif_file, edif_file, json_file;
- bool noccu2, nodffe, nobram, nodram, nomux, flatten, retime, abc2, vpr;
+ bool noccu2, nodffe, nobram, nolutram, nowidelut, flatten, retime, abc2, abc9, dsp, vpr;
void clear_flags() YS_OVERRIDE
{
noccu2 = false;
nodffe = false;
nobram = false;
- nodram = false;
- nomux = false;
+ nolutram = false;
+ nowidelut = false;
flatten = true;
retime = false;
abc2 = false;
vpr = false;
+ abc9 = false;
+ dsp = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
nobram = true;
continue;
}
- if (args[argidx] == "-nodram") {
- nodram = true;
+ if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
+ nolutram = true;
continue;
}
- if (args[argidx] == "-nomux") {
- nomux = true;
+ if (args[argidx] == "-nowidelut" || /*deprecated alias*/ args[argidx] == "-nomux") {
+ nowidelut = true;
continue;
}
if (args[argidx] == "-abc2") {
vpr = true;
continue;
}
+ if (args[argidx] == "-abc9") {
+ abc9 = true;
+ continue;
+ }
+ if (args[argidx] == "-dsp") {
+ dsp = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
+ if (abc9 && retime)
+ log_cmd_error("-retime option not currently compatible with -abc9!\n");
+
log_header(design, "Executing SYNTH_ECP5 pass.\n");
log_push();
{
if (check_label("begin"))
{
- run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
+ run("read_verilog -D_ABC -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
if (check_label("coarse"))
{
- run("synth -run coarse");
+ run("opt_expr");
+ run("opt_clean");
+ run("check");
+ run("opt");
+ run("wreduce");
+ run("peepopt");
+ run("opt_clean");
+ run("share");
+ run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
+ run("opt_expr");
+ run("opt_clean");
+ if (dsp) {
+ run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL18X18");
+ run("clean");
+ run("techmap -map +/ecp5/dsp_map.v");
+ }
+ run("alumacc");
+ run("opt");
+ run("fsm");
+ run("opt -fast");
+ run("memory -nomap");
+ run("opt_clean");
}
- if (!nobram && check_label("bram", "(skip if -nobram)"))
+ if (!nobram && check_label("map_bram", "(skip if -nobram)"))
{
run("memory_bram -rules +/ecp5/bram.txt");
run("techmap -map +/ecp5/brams_map.v");
}
- if (!nodram && check_label("dram", "(skip if -nodram)"))
+ if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
{
- run("memory_bram -rules +/ecp5/dram.txt");
- run("techmap -map +/ecp5/drams_map.v");
+ run("memory_bram -rules +/ecp5/lutram.txt");
+ run("techmap -map +/ecp5/lutrams_map.v");
}
- if (check_label("fine"))
+ if (check_label("map_ffram"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
+ }
+
+ if (check_label("map_gates"))
+ {
if (noccu2)
run("techmap");
else
if (!nodffe)
run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
- run("opt_expr -mux_undef");
+ run("opt_expr -undriven -mux_undef");
run("simplemap");
run("ecp5_ffinit");
}
run("abc", " (only if -abc2)");
}
run("techmap -map +/ecp5/latches_map.v");
- if (nomux)
- run("abc -lut 4");
- else
- run("abc -lut 4:7");
+ if (abc9) {
+ if (nowidelut)
+ run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
+ else
+ run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
+ } else {
+ if (nowidelut)
+ run("abc -lut 4 -dress");
+ else
+ run("abc -lut 4:7 -dress");
+ }
run("clean");
}
projects / yosys.git / blobdiff