output reg Q,
input D,
input CE,
+ (* clkbuf_sink *)
input CLK,
input SR
);
assign ce = CE_POLARITY ? CE : ~CE;
assign sr = SR_POLARITY ? SR : ~SR;
assign d = D_POLARITY ? D : ~D;
-
+
+ initial Q = 1'b0;
+
generate
if (SR_SYNC == 1)
begin
module EFX_GBUFCE(
input CE,
input I,
+ (* clkbuf_driver *)
output O
);
parameter CE_POLARITY = 1'b1;
input [WRITE_WIDTH-1:0] WDATA,
input [WRITE_ADDR_WIDTH-1:0] WADDR,
input WE,
+ (* clkbuf_sink *)
input WCLK,
input WCLKE,
output [READ_WIDTH-1:0] RDATA,
input [READ_ADDR_WIDTH-1:0] RADDR,
input RE,
+ (* clkbuf_sink *)
input RCLK
);
parameter READ_WIDTH = 20;
(WRITE_WIDTH == 10) ? 9 : // 512x10
(WRITE_WIDTH == 5) ? 10 : -1; // 1024x5
-endmodule
\ No newline at end of file
+endmodule