efinix: Nuke efinix_gbuf in favor of clkbufmap.

[yosys.git] / techlibs / efinix / cells_sim.v

diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v
index 8c8f6afaa3e91c77cc5c32f14c1c1888a2452682..22c7bc776dafa88d36d2d2801ae9dffbbb5edeee 100644 (file)
--- a/techlibs/efinix/cells_sim.v
+++ b/techlibs/efinix/cells_sim.v
@@ -5,7 +5,12 @@ module EFX_LUT4(
    input I2,
    input I3
 );
-   parameter LUTMASK  = 16'h0000;
+       parameter LUTMASK = 16'h0000;
+
+       wire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0];
+       wire [3:0] s2 = I2 ?      s3[ 7:4] :      s3[3:0];
+       wire [1:0] s1 = I1 ?      s2[ 3:2] :      s2[1:0];
+       assign O = I0 ? s1[1] : s1[0];     
 endmodule
 
 module EFX_ADD(
@@ -17,12 +22,21 @@ module EFX_ADD(
 );
    parameter I0_POLARITY   = 1;
    parameter I1_POLARITY   = 1;
+
+   wire i0;
+   wire i1;
+
+   assign i0 = I0_POLARITY ? I0 : ~I0;
+   assign i1 = I1_POLARITY ? I1 : ~I1;
+
+   assign {CO, O} = i0 + i1 + CI;
 endmodule
 
 module EFX_FF(
-   output Q,
+   output reg Q,
    input D,
    input CE,
+   (* clkbuf_sink *)
    input CLK,
    input SR
 );
@@ -33,25 +47,83 @@ module EFX_FF(
    parameter SR_VALUE = 0;
    parameter SR_SYNC_PRIORITY = 0;
    parameter D_POLARITY = 1;
+
+   wire clk;
+   wire ce;
+   wire sr;
+   wire d;
+   wire prio;
+   wire sync;
+   wire async;
+
+   assign clk = CLK_POLARITY ? CLK : ~CLK;
+   assign ce = CE_POLARITY ? CE : ~CE;
+   assign sr = SR_POLARITY ? SR : ~SR;
+   assign d = D_POLARITY ? D : ~D;
+
+       initial Q = 1'b0;
+
+   generate
+       if (SR_SYNC == 1) 
+      begin
+         if (SR_SYNC_PRIORITY == 1) 
+         begin
+            always @(posedge clk)
+               if (sr)
+                  Q <= SR_VALUE;
+               else if (ce)
+                  Q <= d;
+         end
+         else
+         begin
+            always @(posedge clk)
+               if (ce)
+               begin
+                  if (sr)
+                     Q <= SR_VALUE;
+                  else
+                     Q <= d;
+               end
+         end
+      end
+      else
+      begin
+         always @(posedge clk or posedge sr)
+            if (sr)
+               Q <= SR_VALUE;
+            else if (ce)
+               Q <= d;
+         
+      end
+   endgenerate
 endmodule
 
 module EFX_GBUFCE(
    input CE,
    input I,
+   (* clkbuf_driver *)
    output O
 );
    parameter CE_POLARITY = 1'b1;
+
+   wire ce;
+   assign ce = CE_POLARITY ? CE : ~CE;
+   
+   assign O = I & ce;
+   
 endmodule
 
 module EFX_RAM_5K(
    input [WRITE_WIDTH-1:0] WDATA,
    input [WRITE_ADDR_WIDTH-1:0] WADDR,
    input WE, 
+   (* clkbuf_sink *)
    input WCLK,
    input WCLKE, 
    output [READ_WIDTH-1:0] RDATA, 
    input [READ_ADDR_WIDTH-1:0] RADDR,
    input RE, 
+   (* clkbuf_sink *)
    input RCLK
 );
    parameter READ_WIDTH = 20;
@@ -104,4 +176,4 @@ module EFX_RAM_5K(
                            (WRITE_WIDTH == 10) ? 9 :  // 512x10
                            (WRITE_WIDTH == 5)  ? 10 : -1; // 1024x5
    
-endmodule
\ No newline at end of file
+endmodule