Merge pull request #1830 from boqwxp/qbfsat

[yosys.git] / techlibs / gowin / arith_map.v

diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v
index 25e789e4ab5446c264f4bb9b8f4c42283ba77dee..b6f9e8c38625c5692e40bce866e53f1c007726a6 100644 (file)
--- a/techlibs/gowin/arith_map.v
+++ b/techlibs/gowin/arith_map.v
@@ -25,30 +25,30 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
    parameter A_WIDTH = 1;
    parameter B_WIDTH = 1;
    parameter Y_WIDTH = 1;
-   
+
    input [A_WIDTH-1:0] A;
    input [B_WIDTH-1:0] B;
    output [Y_WIDTH-1:0] X, Y;
-   
+
    input               CI, BI;
    output [Y_WIDTH-1:0] CO;
-   
+
    wire                _TECHMAP_FAIL_ = Y_WIDTH <= 2;
-   
+
    wire [Y_WIDTH-1:0]  A_buf, B_buf;
    \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
    \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
-   
+
    wire [Y_WIDTH-1:0]  AA = A_buf;
-   wire [Y_WIDTH-1:0]  BB = BI ? ~B_buf : B_buf;
+   wire [Y_WIDTH-1:0]  BB = B_buf;
    wire [Y_WIDTH-1:0]  C = {CO, CI};
-   
+
    genvar              i;
    generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-      ALU #(.ALU_MODE(32'b0))
+      ALU #(.ALU_MODE(2)) // ADDSUB I3 ? add : sub
       alu(.I0(AA[i]),
          .I1(BB[i]),
-         .I3(1'b0),
+         .I3(~BI),
          .CIN(C[i]),
          .COUT(CO[i]),
          .SUM(Y[i])