Merge pull request #412 from azonenberg/reduce-fixes

[yosys.git] / techlibs / greenpak4 / cells_sim.v

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 54e5a423c4e06e8710ebd0f3cdf7dc727c351e19..221bee694fa5b0e9c0c3742036b9074e068f789c 100644 (file)
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -1,65 +1,5 @@
-module GP_DFF(input D, CLK, output reg Q);
-       parameter [0:0] INIT = 1'bx;
-       initial Q = INIT;
-       always @(posedge CLK) begin
-               Q <= D;
-       end
-endmodule
-
-module GP_DFFS(input D, CLK, nSET, output reg Q);
-       parameter [0:0] INIT = 1'bx;
-       initial Q = INIT;
-       always @(posedge CLK, negedge nSET) begin
-               if (!nSET)
-                       Q <= 1'b1;
-               else
-                       Q <= D;
-       end
-endmodule
-
-module GP_DFFR(input D, CLK, nRST, output reg Q);
-       parameter [0:0] INIT = 1'bx;
-       initial Q = INIT;
-       always @(posedge CLK, negedge nRST) begin
-               if (!nRST)
-                       Q <= 1'b0;
-               else
-                       Q <= D;
-       end
-endmodule
-
-module GP_DFFSR(input D, CLK, nSR, output reg Q);
-       parameter [0:0] INIT = 1'bx;
-       parameter [0:0] SRMODE = 1'bx;
-       initial Q = INIT;
-       always @(posedge CLK, negedge nSR) begin
-               if (!nSR)
-                       Q <= SRMODE;
-               else
-                       Q <= D;
-       end
-endmodule
-
-module GP_2LUT(input IN0, IN1, output OUT);
-       parameter [3:0] INIT = 0;
-       assign OUT = INIT[{IN1, IN0}];
-endmodule
-
-module GP_3LUT(input IN0, IN1, IN2, output OUT);
-       parameter [7:0] INIT = 0;
-       assign OUT = INIT[{IN2, IN1, IN0}];
-endmodule
-
-module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
-       parameter [15:0] INIT = 0;
-       assign OUT = INIT[{IN3, IN2, IN1, IN0}];
-endmodule
-
-module GP_VDD(output OUT);
-       assign OUT = 1;
-endmodule
-
-module GP_VSS(output OUT);
-       assign OUT = 0;
-endmodule
+`timescale 1ns/1ps
 
+`include "cells_sim_ams.v"
+`include "cells_sim_digital.v"
+`include "cells_sim_wip.v"