Merge pull request #1765 from YosysHQ/claire/btor_info

[yosys.git] / techlibs / ice40 / brams_map.v

diff --git a/techlibs/ice40/brams_map.v b/techlibs/ice40/brams_map.v
index f3674b4ede9096b2ebca3bcc125bf55f38c8be25..ad3bccd21f45c7015ab94101c4d1942a479c36c4 100644 (file)
--- a/techlibs/ice40/brams_map.v
+++ b/techlibs/ice40/brams_map.v
@@ -7,8 +7,8 @@ module \$__ICE40_RAM4K (
        input  [10:0] WADDR,
        input  [15:0] MASK, WDATA
 );
-       parameter integer READ_MODE = 0;
-       parameter integer WRITE_MODE = 0;
+       parameter [1:0] READ_MODE = 0;
+       parameter [1:0] WRITE_MODE = 0;
        parameter [0:0] NEGCLK_R = 0;
        parameter [0:0] NEGCLK_W = 0;
 
@@ -168,7 +168,7 @@ module \$__ICE40_RAM4K (
 endmodule
 
 
-module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
        parameter [0:0] CLKPOL2 = 1;
        parameter [0:0] CLKPOL3 = 1;
 
@@ -179,6 +179,7 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 
        input [7:0] A1ADDR;
        output [15:0] A1DATA;
+       input A1EN;
 
        input [7:0] B1ADDR;
        input [15:0] B1DATA;
@@ -212,18 +213,18 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
                .RDATA(A1DATA),
                .RADDR(A1ADDR_11),
                .RCLK(CLK2),
-               .RCLKE(1'b1),
+               .RCLKE(A1EN),
                .RE(1'b1),
                .WDATA(B1DATA),
                .WADDR(B1ADDR_11),
                .MASK(~B1EN),
                .WCLK(CLK3),
-               .WCLKE(1'b1),
-               .WE(|B1EN)
+               .WCLKE(|B1EN),
+               .WE(1'b1)
        );
 endmodule
 
-module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
        parameter CFG_ABITS = 9;
        parameter CFG_DBITS = 8;
 
@@ -242,6 +243,7 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 
        input [CFG_ABITS-1:0] A1ADDR;
        output [CFG_DBITS-1:0] A1DATA;
+       input A1EN;
 
        input [CFG_ABITS-1:0] B1ADDR;
        input [CFG_DBITS-1:0] B1DATA;
@@ -297,13 +299,13 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
                .RDATA(A1DATA_16),
                .RADDR(A1ADDR_11),
                .RCLK(CLK2),
-               .RCLKE(1'b1),
+               .RCLKE(A1EN),
                .RE(1'b1),
                .WDATA(B1DATA_16),
                .WADDR(B1ADDR_11),
                .WCLK(CLK3),
-               .WCLKE(1'b1),
-               .WE(|B1EN)
+               .WCLKE(|B1EN),
+               .WE(1'b1)
        );
 endmodule