Comment out SB_MAC16 arrival time for now, need to handle all its modes

[yosys.git] / techlibs / ice40 / cells_sim.v

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 34134d02af838bf856125fe64dda5a1845642f0d..8e5e0358e33e0d80b9a3f7616ab1a1cd688eef79 100644 (file)
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -3,7 +3,7 @@
 // `define SB_DFF_REG reg Q
 
 `define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
-`define ABC_ARRIVAL_LX(TIME) `ifdef ICE40_LX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif
 `define ABC_ARRIVAL_U(TIME)  `ifdef ICE40_U (* abc_arrival=TIME *) `endif
 
 // SiliconBlue IO Cells
@@ -174,11 +174,15 @@ module \$__ICE40_CARRY_WRAPPER (
 endmodule
 
 // Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+//                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+//                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
 
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, D
 );
@@ -188,6 +192,8 @@ endmodule
 
 module SB_DFFE (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, E, D
 );
@@ -198,6 +204,8 @@ endmodule
 
 module SB_DFFSR (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, R, D
 );
@@ -210,6 +218,8 @@ endmodule
 
 module SB_DFFR (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, R, D
 );
@@ -222,6 +232,8 @@ endmodule
 
 module SB_DFFSS (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, S, D
 );
@@ -234,6 +246,8 @@ endmodule
 
 module SB_DFFS (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, S, D
 );
@@ -246,6 +260,8 @@ endmodule
 
 module SB_DFFESR (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, E, R, D
 );
@@ -260,6 +276,8 @@ endmodule
 
 module SB_DFFER (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, E, R, D
 );
@@ -272,6 +290,8 @@ endmodule
 
 module SB_DFFESS (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, E, S, D
 );
@@ -286,6 +306,8 @@ endmodule
 
 module SB_DFFES (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, E, S, D
 );
@@ -300,6 +322,8 @@ endmodule
 
 module SB_DFFN (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, D
 );
@@ -309,6 +333,8 @@ endmodule
 
 module SB_DFFNE (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, E, D
 );
@@ -319,6 +345,8 @@ endmodule
 
 module SB_DFFNSR (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, R, D
 );
@@ -331,6 +359,8 @@ endmodule
 
 module SB_DFFNR (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, R, D
 );
@@ -343,6 +373,8 @@ endmodule
 
 module SB_DFFNSS (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, S, D
 );
@@ -355,6 +387,8 @@ endmodule
 
 module SB_DFFNS (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, S, D
 );
@@ -367,6 +401,8 @@ endmodule
 
 module SB_DFFNESR (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, E, R, D
 );
@@ -381,6 +417,8 @@ endmodule
 
 module SB_DFFNER (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, E, R, D
 );
@@ -393,6 +431,8 @@ endmodule
 
 module SB_DFFNESS (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, E, S, D
 );
@@ -407,6 +447,8 @@ endmodule
 
 module SB_DFFNES (
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output `SB_DFF_REG,
        input C, E, S, D
 );
@@ -421,6 +463,8 @@ endmodule
 
 module SB_RAM40_4K (
        `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+       `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+       `ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
        output [15:0] RDATA,
        input         RCLK, RCLKE, RE,
        input  [10:0] RADDR,
@@ -590,6 +634,8 @@ endmodule
 
 module SB_RAM40_4KNR (
        `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+       `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+       `ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
        output [15:0] RDATA,
        input         RCLKN, RCLKE, RE,
        input  [10:0] RADDR,
@@ -656,6 +702,8 @@ endmodule
 
 module SB_RAM40_4KNW (
        `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+       `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+       `ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
        output [15:0] RDATA,
        input         RCLK, RCLKE, RE,
        input  [10:0] RADDR,
@@ -722,6 +770,8 @@ endmodule
 
 module SB_RAM40_4KNRNW (
        `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+       `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+       `ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
        output [15:0] RDATA,
        input         RCLKN, RCLKE, RE,
        input  [10:0] RADDR,
@@ -792,6 +842,8 @@ module ICESTORM_LC (
        input I0, I1, I2, I3, CIN, CLK, CEN, SR,
        output LO,
        `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
        output O,
        output COUT
 );
@@ -1393,6 +1445,7 @@ module SB_MAC16 (
        input ADDSUBTOP, ADDSUBBOT,
        input OHOLDTOP, OHOLDBOT,
        input CI, ACCUMCI, SIGNEXTIN,
+       //`ABC_ARRIVAL_U(1984)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
        output [31:0] O,
        output CO, ACCUMCO, SIGNEXTOUT
 );