Comment out SB_MAC16 arrival time for now, need to handle all its modes

[yosys.git] / techlibs / ice40 / cells_sim.v

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index c7f3bdad255bb9b1675aedab5c5a2b10d0799cb6..8e5e0358e33e0d80b9a3f7616ab1a1cd688eef79 100644 (file)
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -2,6 +2,10 @@
 `define SB_DFF_REG reg Q = 0
 // `define SB_DFF_REG reg Q
 
+`define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_U(TIME)  `ifdef ICE40_U (* abc_arrival=TIME *) `endif
+
 // SiliconBlue IO Cells
 
 module SB_IO (
@@ -142,15 +146,16 @@ module SB_CARRY (output CO, input I0, I1, CI);
 endmodule
 
 (* abc_box_id = 1, lib_whitebox *)
-module \$__ICE40_FULL_ADDER (
+module \$__ICE40_CARRY_WRAPPER (
        (* abc_carry *)
        output CO,
        output O,
-       input A,
-       input B,
+       input A, B,
        (* abc_carry *)
-       input CI
+       input CI,
+       input I0, I3
 );
+       parameter LUT = 0;
        SB_CARRY carry (
                .I0(A),
                .I1(B),
@@ -158,34 +163,52 @@ module \$__ICE40_FULL_ADDER (
                .CO(CO)
        );
        SB_LUT4 #(
-               //         I0: 1010 1010 1010 1010
-               //         I1: 1100 1100 1100 1100
-               //         I2: 1111 0000 1111 0000
-               //         I3: 1111 1111 0000 0000
-               .LUT_INIT(16'b 0110_1001_1001_0110)
+               .LUT_INIT(LUT)
        ) adder (
-               .I0(1'b0),
+               .I0(I0),
                .I1(A),
                .I2(B),
-               .I3(CI),
+               .I3(I3),
                .O(O)
        );
 endmodule
 
+// Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+//                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+//                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+
 // Positive Edge SiliconBlue FF Cells
 
-module SB_DFF (output `SB_DFF_REG, input C, D);
+module SB_DFF (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, D
+);
        always @(posedge C)
                Q <= D;
 endmodule
 
-module SB_DFFE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFE (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, E, D
+);
        always @(posedge C)
                if (E)
                        Q <= D;
 endmodule
 
-module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFSR (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, R, D
+);
        always @(posedge C)
                if (R)
                        Q <= 0;
@@ -193,7 +216,13 @@ module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
                        Q <= D;
 endmodule
 
-module SB_DFFR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFR (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, R, D
+);
        always @(posedge C, posedge R)
                if (R)
                        Q <= 0;
@@ -201,7 +230,13 @@ module SB_DFFR (output `SB_DFF_REG, input C, R, D);
                        Q <= D;
 endmodule
 
-module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFSS (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, S, D
+);
        always @(posedge C)
                if (S)
                        Q <= 1;
@@ -209,7 +244,13 @@ module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
                        Q <= D;
 endmodule
 
-module SB_DFFS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFS (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, S, D
+);
        always @(posedge C, posedge S)
                if (S)
                        Q <= 1;
@@ -217,7 +258,13 @@ module SB_DFFS (output `SB_DFF_REG, input C, S, D);
                        Q <= D;
 endmodule
 
-module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFESR (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, E, R, D
+);
        always @(posedge C)
                if (E) begin
                        if (R)
@@ -227,7 +274,13 @@ module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
                end
 endmodule
 
-module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFER (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, E, R, D
+);
        always @(posedge C, posedge R)
                if (R)
                        Q <= 0;
@@ -235,7 +288,13 @@ module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
                        Q <= D;
 endmodule
 
-module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFESS (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, E, S, D
+);
        always @(posedge C)
                if (E) begin
                        if (S)
@@ -245,7 +304,13 @@ module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
                end
 endmodule
 
-module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFES (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, E, S, D
+);
        always @(posedge C, posedge S)
                if (S)
                        Q <= 1;
@@ -255,18 +320,36 @@ endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
-module SB_DFFN (output `SB_DFF_REG, input C, D);
+module SB_DFFN (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, D
+);
        always @(negedge C)
                Q <= D;
 endmodule
 
-module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFNE (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, E, D
+);
        always @(negedge C)
                if (E)
                        Q <= D;
 endmodule
 
-module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNSR (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, R, D
+);
        always @(negedge C)
                if (R)
                        Q <= 0;
@@ -274,7 +357,13 @@ module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
                        Q <= D;
 endmodule
 
-module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNR (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, R, D
+);
        always @(negedge C, posedge R)
                if (R)
                        Q <= 0;
@@ -282,7 +371,13 @@ module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
                        Q <= D;
 endmodule
 
-module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNSS (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, S, D
+);
        always @(negedge C)
                if (S)
                        Q <= 1;
@@ -290,7 +385,13 @@ module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
                        Q <= D;
 endmodule
 
-module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNS (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, S, D
+);
        always @(negedge C, posedge S)
                if (S)
                        Q <= 1;
@@ -298,7 +399,13 @@ module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
                        Q <= D;
 endmodule
 
-module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNESR (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, E, R, D
+);
        always @(negedge C)
                if (E) begin
                        if (R)
@@ -308,7 +415,13 @@ module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
                end
 endmodule
 
-module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNER (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, E, R, D
+);
        always @(negedge C, posedge R)
                if (R)
                        Q <= 0;
@@ -316,7 +429,13 @@ module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
                        Q <= D;
 endmodule
 
-module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNESS (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, E, S, D
+);
        always @(negedge C)
                if (E) begin
                        if (S)
@@ -326,7 +445,13 @@ module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
                end
 endmodule
 
-module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNES (
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output `SB_DFF_REG,
+       input C, E, S, D
+);
        always @(negedge C, posedge S)
                if (S)
                        Q <= 1;
@@ -337,6 +462,9 @@ endmodule
 // SiliconBlue RAM Cells
 
 module SB_RAM40_4K (
+       `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+       `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+       `ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
        output [15:0] RDATA,
        input         RCLK, RCLKE, RE,
        input  [10:0] RADDR,
@@ -505,6 +633,9 @@ module SB_RAM40_4K (
 endmodule
 
 module SB_RAM40_4KNR (
+       `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+       `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+       `ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
        output [15:0] RDATA,
        input         RCLKN, RCLKE, RE,
        input  [10:0] RADDR,
@@ -570,6 +701,9 @@ module SB_RAM40_4KNR (
 endmodule
 
 module SB_RAM40_4KNW (
+       `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+       `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+       `ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
        output [15:0] RDATA,
        input         RCLK, RCLKE, RE,
        input  [10:0] RADDR,
@@ -635,6 +769,9 @@ module SB_RAM40_4KNW (
 endmodule
 
 module SB_RAM40_4KNRNW (
+       `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+       `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+       `ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
        output [15:0] RDATA,
        input         RCLKN, RCLKE, RE,
        input  [10:0] RADDR,
@@ -703,7 +840,12 @@ endmodule
 
 module ICESTORM_LC (
        input I0, I1, I2, I3, CIN, CLK, CEN, SR,
-       output LO, O, COUT
+       output LO,
+       `ABC_ARRIVAL_HX(540)
+       `ABC_ARRIVAL_LP(796)
+       `ABC_ARRIVAL_U(1391)
+       output O,
+       output COUT
 );
        parameter [15:0] LUT_INIT = 0;
 
@@ -1303,6 +1445,7 @@ module SB_MAC16 (
        input ADDSUBTOP, ADDSUBBOT,
        input OHOLDTOP, OHOLDBOT,
        input CI, ACCUMCI, SIGNEXTIN,
+       //`ABC_ARRIVAL_U(1984)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
        output [31:0] O,
        output CO, ACCUMCO, SIGNEXTOUT
 );