Merge pull request #1765 from YosysHQ/claire/btor_info

[yosys.git] / techlibs / ice40 / synth_ice40.cc

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 08aa8b4d8ff220d00e622b36ce3ba9a8e1e63177..59ada8bae69b91fe7270126ea8a32fd321909bc5 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -96,9 +96,9 @@ struct SynthIce40Pass : public ScriptPass
                log("    -abc9\n");
                log("        use new ABC9 flow (EXPERIMENTAL)\n");
                log("\n");
-        log("    -flowmap\n");
-        log("        use FlowMap LUT techmapping instead of abc (EXPERIMENTAL)\n");
-        log("\n");
+               log("    -flowmap\n");
+               log("        use FlowMap LUT techmapping instead of abc (EXPERIMENTAL)\n");
+               log("\n");
                log("\n");
                log("The following commands are executed by this synthesis command:\n");
                help_script();
@@ -126,7 +126,7 @@ struct SynthIce40Pass : public ScriptPass
                abc2 = false;
                vpr = false;
                abc9 = false;
-        flowmap = false;
+               flowmap = false;
                device_opt = "hx";
        }
 
@@ -251,16 +251,16 @@ struct SynthIce40Pass : public ScriptPass
 
        void script() YS_OVERRIDE
        {
+               std::string define;
+               if (device_opt == "lp")
+                       define = "-D ICE40_LP";
+               else if (device_opt == "u")
+                       define = "-D ICE40_U";
+               else
+                       define = "-D ICE40_HX";
                if (check_label("begin"))
                {
-                       std::string define;
-                       if (device_opt == "lp")
-                               define = "-D ICE40_LP";
-                       else if (device_opt == "u")
-                               define = "-D ICE40_U";
-                       else
-                               define = "-D ICE40_HX";
-                       run("read_verilog " + define + " -lib +/ice40/cells_sim.v");
+                       run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v");
                        run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
                        run("proc");
                }
@@ -345,6 +345,7 @@ struct SynthIce40Pass : public ScriptPass
                        if (min_ce_use >= 0) {
                                run("opt_merge");
                                run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
+                               run("simplemap t:$dff");
                        }
                        run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
                        run("opt_expr -mux_undef");
@@ -370,7 +371,7 @@ struct SynthIce40Pass : public ScriptPass
                        }
                        if (!noabc) {
                                if (abc9) {
-                                       run("read_verilog -icells -lib +/ice40/abc9_model.v");
+                                       run("read_verilog " + define + " -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");
                                        int wire_delay;
                                        if (device_opt == "lp")
                                                wire_delay = 400;
@@ -378,7 +379,7 @@ struct SynthIce40Pass : public ScriptPass
                                                wire_delay = 750;
                                        else
                                                wire_delay = 250;
-                                       run(stringf("abc9 -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()));
+                                       run(stringf("abc9 -W %d", wire_delay));
                                }
                                else
                                        run("abc -dress -lut 4", "(skip if -noabc)");