module RAM32X1D (
output DPO, SPO,
- input D,
- input WCLK,
- input WE,
- input A0, A1, A2, A3, A4,
- input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
+ (* techmap_autopurge *) input D,
+ (* techmap_autopurge *) input WCLK,
+ (* techmap_autopurge *) input WE,
+ (* techmap_autopurge *) input A0, A1, A2, A3, A4,
+ (* techmap_autopurge *) input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
parameter INIT = 32'h0;
parameter IS_WCLK_INVERTED = 1'b0;
module RAM64X1D (
output DPO, SPO,
- input D,
- input WCLK,
- input WE,
- input A0, A1, A2, A3, A4, A5,
- input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
+ (* techmap_autopurge *) input D,
+ (* techmap_autopurge *) input WCLK,
+ (* techmap_autopurge *) input WE,
+ (* techmap_autopurge *) input A0, A1, A2, A3, A4, A5,
+ (* techmap_autopurge *) input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
parameter INIT = 64'h0;
parameter IS_WCLK_INVERTED = 1'b0;
module RAM128X1D (
output DPO, SPO,
- input D,
- input WCLK,
- input WE,
- input [6:0] A, DPRA
+ (* techmap_autopurge *) input D,
+ (* techmap_autopurge *) input WCLK,
+ (* techmap_autopurge *) input WE,
+ (* techmap_autopurge *) input [6:0] A, DPRA
);
parameter INIT = 128'h0;
parameter IS_WCLK_INVERTED = 1'b0;
module SRL16E (
output Q,
- input A0, A1, A2, A3, CE, CLK, D
+ (* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D
);
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
module SRLC32E (
output Q,
output Q31,
- input [4:0] A,
- input CE, CLK, D
+ (* techmap_autopurge *) input [4:0] A,
+ (* techmap_autopurge *) input CE, CLK, D
);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
output PATTERNDETECT,
output [47:0] PCOUT,
output UNDERFLOW,
- input signed [29:0] A,
- input [29:0] ACIN,
- input [3:0] ALUMODE,
- input signed [17:0] B,
- input [17:0] BCIN,
- input [47:0] C,
- input CARRYCASCIN,
- input CARRYIN,
- input [2:0] CARRYINSEL,
- input CEA1,
- input CEA2,
- input CEAD,
- input CEALUMODE,
- input CEB1,
- input CEB2,
- input CEC,
- input CECARRYIN,
- input CECTRL,
- input CED,
- input CEINMODE,
- input CEM,
- input CEP,
- input CLK,
- input [24:0] D,
- input [4:0] INMODE,
- input MULTSIGNIN,
- input [6:0] OPMODE,
- input [47:0] PCIN,
- input RSTA,
- input RSTALLCARRYIN,
- input RSTALUMODE,
- input RSTB,
- input RSTC,
- input RSTCTRL,
- input RSTD,
- input RSTINMODE,
- input RSTM,
- input RSTP
+ (* techmap_autopurge *) input signed [29:0] A,
+ (* techmap_autopurge *) input [29:0] ACIN,
+ (* techmap_autopurge *) input [3:0] ALUMODE,
+ (* techmap_autopurge *) input signed [17:0] B,
+ (* techmap_autopurge *) input [17:0] BCIN,
+ (* techmap_autopurge *) input [47:0] C,
+ (* techmap_autopurge *) input CARRYCASCIN,
+ (* techmap_autopurge *) input CARRYIN,
+ (* techmap_autopurge *) input [2:0] CARRYINSEL,
+ (* techmap_autopurge *) input CEA1,
+ (* techmap_autopurge *) input CEA2,
+ (* techmap_autopurge *) input CEAD,
+ (* techmap_autopurge *) input CEALUMODE,
+ (* techmap_autopurge *) input CEB1,
+ (* techmap_autopurge *) input CEB2,
+ (* techmap_autopurge *) input CEC,
+ (* techmap_autopurge *) input CECARRYIN,
+ (* techmap_autopurge *) input CECTRL,
+ (* techmap_autopurge *) input CED,
+ (* techmap_autopurge *) input CEINMODE,
+ (* techmap_autopurge *) input CEM,
+ (* techmap_autopurge *) input CEP,
+ (* techmap_autopurge *) input CLK,
+ (* techmap_autopurge *) input [24:0] D,
+ (* techmap_autopurge *) input [4:0] INMODE,
+ (* techmap_autopurge *) input MULTSIGNIN,
+ (* techmap_autopurge *) input [6:0] OPMODE,
+ (* techmap_autopurge *) input [47:0] PCIN,
+ (* techmap_autopurge *) input RSTA,
+ (* techmap_autopurge *) input RSTALLCARRYIN,
+ (* techmap_autopurge *) input RSTALUMODE,
+ (* techmap_autopurge *) input RSTB,
+ (* techmap_autopurge *) input RSTC,
+ (* techmap_autopurge *) input RSTCTRL,
+ (* techmap_autopurge *) input RSTD,
+ (* techmap_autopurge *) input RSTINMODE,
+ (* techmap_autopurge *) input RSTM,
+ (* techmap_autopurge *) input RSTP
);
parameter integer ACASCREG = 1;
parameter integer ADREG = 1;
);
"""
- generate
- if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
- wire [29:0] iA;
- wire [17:0] iB;
- wire [47:0] iC;
- wire [24:0] iD;
+ wire [29:0] iA;
+ wire [17:0] iB;
+ wire [47:0] iC;
+ wire [24:0] iD;
- wire pA, pB, pC, pD, pAD, pM, pP;
- wire [47:0] oP, oPCOUT;
+ wire pA, pB, pC, pD, pAD, pM, pP;
+ wire [47:0] oP, mP;
+ wire [47:0] oPCOUT, mPCOUT;
+ generate
+ if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
// Disconnect the A-input if MREG is enabled, since
// combinatorial path is broken
if (AREG == 0 && MREG == 0 && PREG == 0)
- assign iA = A;
+ assign iA = A, pA = 1'bx;
else
- \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
+ \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
if (BREG == 0 && MREG == 0 && PREG == 0)
- assign iB = B;
+ assign iB = B, pB = 1'bx;
else
- \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
+ \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
if (CREG == 0 && PREG == 0)
- assign iC = C;
+ assign iC = C, pC = 1'bx;
else
- \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
+ \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
if (DREG == 0)
assign iD = D;
else if (techmap_guard)
$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
+ assign pD = 1'bx;
if (ADREG == 1 && techmap_guard)
- $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
+ $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
+ assign pAD = 1'bx;
if (PREG == 0) begin
+ assign pP = 1'bx;
if (MREG == 1)
- \$__ABC_DSP48E1_REG rM (.Q(pM));
+ \$__ABC_REG rM (.Q(pM));
+ else
+ assign pM = 1'bx;
end
- else
- \$__ABC_DSP48E1_REG rP (.Q(pP));
+ else begin
+ \$__ABC_REG rP (.Q(pP));
+ assign pM = 1'bx;
+ end
+ if (MREG == 0 && PREG == 0)
+ assign mP = oP, mPCOUT = oPCOUT;
+ else
+ assign mP = 1'bx, mPCOUT = 1'bx;
\$__ABC_DSP48E1_MULT_P_MUX muxP (
- .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
+ .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
);
\$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
- .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
+ .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
);
`DSP48E1_INST(\$__ABC_DSP48E1_MULT )
end
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
- wire [29:0] iA;
- wire [17:0] iB;
- wire [47:0] iC;
- wire [24:0] iD;
-
- wire pA, pB, pC, pD, pAD, pM, pP;
- wire [47:0] oP, oPCOUT;
-
// Disconnect the A-input if MREG is enabled, since
// combinatorial path is broken
if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0)
- assign iA = A;
+ assign iA = A, pA = 1'bx;
else
- \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
+ \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
if (BREG == 0 && MREG == 0 && PREG == 0)
- assign iB = B;
+ assign iB = B, pB = 1'bx;
else
- \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
+ \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
if (CREG == 0 && PREG == 0)
- assign iC = C;
+ assign iC = C, pC = 1'bx;
else
- \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
+ \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
if (DREG == 0 && ADREG == 0)
- assign iD = D;
+ assign iD = D, pD = 1'bx;
else
- \$__ABC_DSP48E1_REG rD (.I(D), .O(iD), .Q(pD));
+ \$__ABC_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD));
if (PREG == 0) begin
if (MREG == 1)
- \$__ABC_DSP48E1_REG rM (.Q(pM));
- else if (ADREG == 1)
- \$__ABC_DSP48E1_REG rAD (.Q(pAD));
+ \$__ABC_REG rM (.Q(pM));
+ else begin
+ assign pM = 1'bx;
+ if (ADREG == 1)
+ \$__ABC_REG rAD (.Q(pAD));
+ else
+ assign pAD = 1'bx;
+ end
end
else
- \$__ABC_DSP48E1_REG rP (.Q(pP));
+ \$__ABC_REG rP (.Q(pP));
+ if (MREG == 0 && PREG == 0)
+ assign mP = oP, mPCOUT = oPCOUT;
+ else
+ assign mP = 1'bx, mPCOUT = 1'bx;
\$__ABC_DSP48E1_MULT_DPORT_P_MUX muxP (
- .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
+ .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
);
\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
- .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
+ .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
);
`DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT )
end
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
- wire [29:0] iA;
- wire [17:0] iB;
- wire [47:0] iC;
- wire [24:0] iD;
-
- wire pA, pB, pC, pD, pAD, pM, pP;
- wire [47:0] oP, oPCOUT;
-
// Disconnect the A-input if MREG is enabled, since
// combinatorial path is broken
if (AREG == 0 && PREG == 0)
- assign iA = A;
+ assign iA = A, pA = 1'bx;
else
- \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
+ \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
if (BREG == 0 && PREG == 0)
- assign iB = B;
+ assign iB = B, pB = 1'bx;
else
- \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
+ \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
if (CREG == 0 && PREG == 0)
- assign iC = C;
+ assign iC = C, pC = 1'bx;
else
- \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
+ \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
if (MREG == 1 && techmap_guard)
- $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
+ $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
+ assign pM = 1'bx;
if (DREG == 1 && techmap_guard)
$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
+ assign pD = 1'bx;
if (ADREG == 1 && techmap_guard)
$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
+ assign pAD = 1'bx;
if (PREG == 1)
- \$__ABC_DSP48E1_REG rP (.Q(pP));
+ \$__ABC_REG rP (.Q(pP));
+ else
+ assign pP = 1'bx;
+ if (MREG == 0 && PREG == 0)
+ assign mP = oP, mPCOUT = oPCOUT;
+ else
+ assign mP = 1'bx, mPCOUT = 1'bx;
\$__ABC_DSP48E1_P_MUX muxP (
- .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
+ .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
);
\$__ABC_DSP48E1_PCOUT_MUX muxPCOUT (
- .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
+ .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
);
`DSP48E1_INST(\$__ABC_DSP48E1 )
projects / yosys.git / blobdiff