Use LUT delays for dist RAM delays

[yosys.git] / techlibs / xilinx / abc_xc7.box

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 0a6a6eaf0fa5b7160b20e58b88865841151b05b0..8c046cdbcc9083cf7c53f755ac5057d886c538a4 100644 (file)
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -1,5 +1,8 @@
 # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
 
+# NB: Inputs/Outputs must be ordered alphabetically
+#     (with exceptions for carry in/out)
+
 # F7BMUX slower than F7AMUX
 # Inputs: I0 I1 S0
 # Outputs: O
@@ -26,3 +29,17 @@ CARRY4 3 1 10 8
 494 465 445 -   -   433 469 -   -   157
 592 540 520 356 -   512 548 292 -   228
 580 526 507 398 385 508 528 378 380 114
+
+# SLICEM/A6LUT
+# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
+# Outputs: DPO SPO
+RAM64X1D 4 0 15 2
+-   -   -   -   -   -   - 642 631 472 407 238 127 - -
+642 631 472 407 238 127 - -   -   -   -   -   -   - -
+
+# SLICEM/A6LUT + F7[AB]MUX
+# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
+# Outputs: DPO SPO
+RAM128X1D 5 0 17 2
+-    -    -   -   -   -   -   - 1009 998 839 774 605 494 450 - -
+1047 1036 877 812 643 532 478 - -    -   -   -   -   -   -   - -