Merge branch 'master' into mwk/xilinx_bufgmap

[yosys.git] / techlibs / xilinx / cells_sim.v

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index f1e019d1e1b82b8a572efb5e3d1786f13e28db06..aeef7f8851ba3707fb0b94cd2af7a3024207b687 100644 (file)
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -343,7 +343,7 @@ module RAM64X1D (
   (* clkbuf_sink *)
   input  WCLK,
   (* abc_scc_break *)
-  input WE,
+  input  WE,
   input  A0, A1, A2, A3, A4, A5,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );