Merge remote-tracking branch 'origin/master' into xc7dsp

[yosys.git] / techlibs / xilinx / dsp_map.v

diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v
index 4faa204aa4a3cb54a244edb2de10d8c003db6622..a4256eb928cb2bcb6c169e71af4805be410aa620 100644 (file)
--- a/techlibs/xilinx/dsp_map.v
+++ b/techlibs/xilinx/dsp_map.v
@@ -1,4 +1,10 @@
-module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT);
+module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
+       parameter A_SIGNED = 0;
+       parameter B_SIGNED = 0;
+       parameter A_WIDTH = 0;
+       parameter B_WIDTH = 0;
+       parameter Y_WIDTH = 0;
+
        wire [47:0] P_48;
        DSP48E1 #(
                // Disable all registers
@@ -17,16 +23,19 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT);
                .INMODEREG(0),
                .MREG(0),
                .OPMODEREG(0),
-               .PREG(0)
+               .PREG(0),
+               .USE_MULT("MULTIPLY"),
+               .USE_SIMD("ONE48"),
+               .USE_DPORT("FALSE")
        ) _TECHMAP_REPLACE_ (
                //Data path
-               .A({5'b0, A}),
+               .A({{5{A[24]}}, A}),
                .B(B),
                .C(48'b0),
-               .D(24'b0),
+               .D(25'b0),
                .P(P_48),
 
-               .INMODE(4'b0000),
+               .INMODE(5'b00000),
                .ALUMODE(4'b0000),
                .OPMODE(7'b000101),
                .CARRYINSEL(3'b000),
@@ -36,5 +45,5 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT);
                .PCIN(48'b0),
                .CARRYIN(1'b0)
        );
-       assign OUT = P_48;
+       assign Y = P_48;
 endmodule