Add support for synth_xilinx -abc9 and ignore abc9 -dress opt

[yosys.git] / techlibs / xilinx / synth_xilinx.cc

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 60cfde604ca29cfc7b264073f332456e562c9d6f..090bcce857c45f5a1bc791de91e1c47146d26b96 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -63,10 +63,10 @@ struct SynthXilinxPass : public Pass
                log("        generate an output netlist (and BLIF file) suitable for VPR\n");
                log("        (this feature is experimental and incomplete)\n");
                log("\n");
-               log("    -no-brams\n");
+               log("    -nobram\n");
                log("        disable infering of block rams\n");
                log("\n");
-               log("    -no-drams\n");
+               log("    -nodram\n");
                log("        disable infering of distributed rams\n");
                log("\n");
                log("    -run <from_label>:<to_label>\n");
@@ -80,6 +80,9 @@ struct SynthXilinxPass : public Pass
                log("    -retime\n");
                log("        run 'abc' with -dff option\n");
                log("\n");
+               log("    -abc9\n");
+               log("        use abc9 instead of abc\n");
+               log("\n");
                log("\n");
                log("The following commands are executed by this synthesis command:\n");
                log("\n");
@@ -96,11 +99,11 @@ struct SynthXilinxPass : public Pass
                log("    coarse:\n");
                log("        synth -run coarse\n");
                log("\n");
-               log("    bram: (only executed when '-no-brams' is not given)\n");
+               log("    bram: (only executed when '-nobram' is not given)\n");
                log("        memory_bram -rules +/xilinx/brams.txt\n");
                log("        techmap -map +/xilinx/brams_map.v\n");
                log("\n");
-               log("    dram: (only executed when '-no-drams' is not given)\n");
+               log("    dram: (only executed when '-nodram' is not given)\n");
                log("        memory_bram -rules +/xilinx/drams.txt\n");
                log("        techmap -map +/xilinx/drams_map.v\n");
                log("\n");
@@ -120,7 +123,8 @@ struct SynthXilinxPass : public Pass
                log("\n");
                log("    map_cells:\n");
                log("        techmap -map +/xilinx/cells_map.v\n");
-               log("        dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT\n");
+               log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
+               log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
                log("        clean\n");
                log("\n");
                log("    check:\n");
@@ -141,11 +145,12 @@ struct SynthXilinxPass : public Pass
                std::string edif_file;
                std::string blif_file;
                std::string run_from, run_to;
+               std::string abc = "abc";
                bool flatten = false;
                bool retime = false;
                bool vpr = false;
-               bool noBrams = false;
-               bool noDrams = false;
+               bool nobram = false;
+               bool nodram = false;
 
                size_t argidx;
                for (argidx = 1; argidx < args.size(); argidx++)
@@ -182,12 +187,16 @@ struct SynthXilinxPass : public Pass
                                vpr = true;
                                continue;
                        }
-                       if (args[argidx] == "-no-brams") {
-                               noBrams = true;
+                       if (args[argidx] == "-nobram") {
+                               nobram = true;
+                               continue;
+                       }
+                       if (args[argidx] == "-nodram") {
+                               nodram = true;
                                continue;
                        }
-                       if (args[argidx] == "-no-drams") {
-                               noDrams = true;
+                       if (args[argidx] == "-abc9") {
+                               abc = "abc9";
                                continue;
                        }
                        break;
@@ -212,7 +221,7 @@ struct SynthXilinxPass : public Pass
 
                        Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v");
 
-                       if (!noBrams) {
+                       if (!nobram) {
                                Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
                        }
 
@@ -232,7 +241,7 @@ struct SynthXilinxPass : public Pass
 
                if (check_label(active, run_from, run_to, "bram"))
                {
-                       if (!noBrams) {
+                       if (!nobram) {
                                Pass::call(design, "memory_bram -rules +/xilinx/brams.txt");
                                Pass::call(design, "techmap -map +/xilinx/brams_map.v");
                        }
@@ -240,7 +249,7 @@ struct SynthXilinxPass : public Pass
 
                if (check_label(active, run_from, run_to, "dram"))
                {
-                       if (!noDrams) {
+                       if (!nodram) {
                                Pass::call(design, "memory_bram -rules +/xilinx/drams.txt");
                                Pass::call(design, "techmap -map +/xilinx/drams_map.v");
                        }
@@ -266,7 +275,7 @@ struct SynthXilinxPass : public Pass
 
                if (check_label(active, run_from, run_to, "map_luts"))
                {
-                       Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+                       Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
                        Pass::call(design, "clean");
                        Pass::call(design, "techmap -map +/xilinx/lut_map.v");
                }
@@ -274,7 +283,8 @@ struct SynthXilinxPass : public Pass
                if (check_label(active, run_from, run_to, "map_cells"))
                {
                        Pass::call(design, "techmap -map +/xilinx/cells_map.v");
-                       Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT");
+                       Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+                                       "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
                        Pass::call(design, "clean");
                }
 
@@ -288,7 +298,7 @@ struct SynthXilinxPass : public Pass
                if (check_label(active, run_from, run_to, "edif"))
                {
                        if (!edif_file.empty())
-                               Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
+                               Pass::call(design, stringf("write_edif -pvector bra %s", edif_file.c_str()));
                }
                if (check_label(active, run_from, run_to, "blif"))
                {