log(" -top <module>\n");
log(" use the specified module as top module\n");
log("\n");
- log(" -arch {xcup|xcu|xc7|xc6s}\n");
+ log(" -family {xcup|xcu|xc7|xc6s}\n");
log(" run synthesis for the specified Xilinx architecture\n");
+ log(" generate the synthesis netlist for the specified family.\n");
log(" default: xc7\n");
log("\n");
log(" -edif <file>\n");
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
log(" (this feature is experimental and incomplete)\n");
log("\n");
- log(" -nocarry\n");
- log(" disable inference of carry chains\n");
- log("\n");
log(" -nobram\n");
log(" disable inference of block rams\n");
log("\n");
log(" -nowidelut\n");
log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
log("\n");
+ log(" -widemux <int>\n");
+ log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
+ log(" above this number of inputs (minimum value 2, recommended value >= 5).\n");
+ log(" default: 0 (no inference)\n");
+ log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). an empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n");
log("\n");
}
- std::string top_opt, edif_file, blif_file, abc, arch;
- bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut;
+ std::string top_opt, edif_file, blif_file, family;
+ bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
+ int widemux;
void clear_flags() YS_OVERRIDE
{
top_opt = "-auto-top";
edif_file.clear();
blif_file.clear();
- abc = "abc";
+ family = "xc7";
flatten = false;
retime = false;
vpr = false;
nosrl = false;
nocarry = false;
nowidelut = false;
- arch = "xc7";
+ abc9 = false;
+ widemux = 0;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
top_opt = "-top " + args[++argidx];
continue;
}
- if (args[argidx] == "-arch" && argidx+1 < args.size()) {
- arch = args[++argidx];
+ if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
+ family = args[++argidx];
continue;
}
if (args[argidx] == "-edif" && argidx+1 < args.size()) {
nosrl = true;
continue;
}
+ if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
+ widemux = std::stoi(args[++argidx]);
+ continue;
+ }
if (args[argidx] == "-abc9") {
- abc = "abc9";
+ abc9 = true;
continue;
}
break;
}
extra_args(args, argidx, design);
- if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s")
- log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str());
+ if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
+ log_cmd_error("Invalid Xilinx -family setting: %s\n", family.c_str());
+
+ if (widemux != 0 && widemux < 2)
+ log_cmd_error("-widemux value must be 0 or >= 2.\n");
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
{
if (check_label("begin")) {
if (vpr)
- run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+ run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
else
- run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v");
+ run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
run("read_verilog -lib +/xilinx/cells_xtra.v");
run(stringf("hierarchy -check %s", top_opt.c_str()));
}
- if (check_label("flatten", "(with '-flatten' only)")) {
- if (flatten || help_mode) {
- run("proc");
- run("flatten");
- }
- }
-
if (check_label("coarse")) {
- run("synth -run coarse");
+ if (help_mode)
+ run("synth -keepdc -run coarse [-flatten]", "(with '-flatten')");
+ else
+ run("synth -keepdc -run coarse" + std::string(flatten ? "" : " -flatten"), "(with '-flatten')");
+
+ if (widemux > 0 || help_mode)
+ run("muxpack", " ('-widemux' only)");
// shregmap -tech xilinx can cope with $shiftx and $mux
// cells for identifying variable-length shift registers,
// so attempt to convert $pmux-es to the former
- if (!nosrl || help_mode)
- run("pmux2shiftx", "(skip if '-nosrl')");
-
- // Run a number of peephole optimisations, including one
- // that optimises $mul cells driving $shiftx's B input
- // and that aids wide mux analysis
- run("peepopt");
+ // Also: wide multiplexer inference benefits from this too
+ if (!(nosrl && widemux == 0) || help_mode)
+ run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
}
if (check_label("bram", "(skip if '-nobram')")) {
}
if (check_label("fine")) {
- run("opt -fast -full");
+ if (widemux > 0)
+ run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover
+ // performs less efficiently
+ else
+ run("opt -fast -full");
run("memory_map");
run("dffsr2dff");
run("dff2dffe");
+ if (help_mode) {
+ run("simplemap t:$mux", " ('-widemux' only)");
+ run("muxcover <internal options>, ('-widemux' only)");
+ }
+ else if (widemux > 0) {
+ run("simplemap t:$mux");
+ constexpr int cost_mux2 = 100;
+ std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2);
+ switch (widemux) {
+ case 2: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2+1, cost_mux2+2, cost_mux2+3); break;
+ case 3:
+ case 4: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-2, cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
+ case 5:
+ case 6:
+ case 7:
+ case 8: muxcover_args += stringf(" -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
+ case 9:
+ case 10:
+ case 11:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ default: muxcover_args += stringf(" -mux16=%d", cost_mux2*(widemux-1)-1); break;
+ }
+ run("muxcover " + muxcover_args);
+ }
run("opt -full");
if (!nosrl || help_mode) {
// shregmap operates on bit-level flops, not word-level,
// so break those down here
- run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')");
+ run("simplemap t:$dff t:$dffe", " (skip if '-nosrl')");
// shregmap with '-tech xilinx' infers variable length shift regs
run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
}
- std::string techmap_files = " -map +/techmap.v";
+ std::string techmap_args = " -map +/techmap.v";
if (help_mode)
- techmap_files += " [-map +/xilinx/arith_map.v]";
+ techmap_args += " [-map +/xilinx/mux_map.v]";
+ else if (widemux > 0)
+ techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", widemux);
+ if (help_mode)
+ techmap_args += " [-map +/xilinx/arith_map.v]";
else if (!nocarry) {
- techmap_files += " -map +/xilinx/arith_map.v";
+ techmap_args += " -map +/xilinx/arith_map.v";
if (vpr)
- techmap_files += " -D _EXPLICIT_CARRY";
- else if (abc == "abc9")
- techmap_files += " -D _CLB_CARRY";
+ techmap_args += " -D _EXPLICIT_CARRY";
+ else if (abc9)
+ techmap_args += " -D _CLB_CARRY";
}
- run("techmap " + techmap_files);
+ run("techmap " + techmap_args);
run("opt -fast");
}
if (check_label("map_cells")) {
- run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
+ std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
+ if (widemux > 0)
+ techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
+ run("techmap " + techmap_args);
run("clean");
}
if (check_label("map_luts")) {
run("opt_expr -mux_undef");
- if (abc == "abc9")
- run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -dff" : ""));
- else if (help_mode)
+ if (help_mode)
run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(skip if 'nowidelut', only for '-retime')");
- else if (nowidelut)
- run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
- else
- run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+ else if (abc9) {
+ if (family != "xc7")
+ log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
+ if (nowidelut)
+ run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
+ else
+ run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
+ }
+ else {
+ if (nowidelut)
+ run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
+ else
+ run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+ }
run("clean");
// This shregmap call infers fixed length shift registers after abc
projects / yosys.git / blobdiff