Missing space

[yosys.git] / techlibs / xilinx / synth_xilinx.cc

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 5af27dea8a6cb530aff0a73d634286af6ff9565d..e822d9b7ef08f8160cc9c2e11a8799ae18935c81 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -83,6 +83,7 @@ struct SynthXilinxPass : public ScriptPass
                log("\n");
                log("    -nodsp\n");
                log("        do not use DSP48E1s to implement multipliers and associated logic\n");
+               log("\n");
                log("    -iopad\n");
                log("        enable I/O buffer insertion (selected automatically by -ise)\n");
                log("\n");
@@ -273,11 +274,19 @@ struct SynthXilinxPass : public ScriptPass
 
        void script() YS_OVERRIDE
        {
+               std::string ff_map_file;
+               if (help_mode)
+                       ff_map_file = "+/xilinx/xc6s_ff_map.v";
+               else if (family == "xc6s")
+                       ff_map_file = "+/xilinx/xc6s_ff_map.v";
+               else
+                       ff_map_file = "+/xilinx/xc7_ff_map.v";
+
                if (check_label("begin")) {
                        if (vpr)
-                               run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+                               run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
                        else
-                               run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
+                               run("read_verilog -lib +/xilinx/cells_sim.v");
 
                        run("read_verilog -lib +/xilinx/cells_xtra.v");
 
@@ -321,14 +330,12 @@ struct SynthXilinxPass : public ScriptPass
                        run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
                }
 
-               if (check_label("dsp")) {
+               if (check_label("map_dsp"), "(skip if '-nodsp')") {
                        if (!nodsp || help_mode) {
                                // NB: Xilinx multipliers are signed only
-                               run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
-                               run("opt_expr -fine", "                 (skip if '-nodsp')");
-                               run("wreduce", "                        (skip if '-nodsp')");
-                               run("xilinx_dsp", "                     (skip if '-nodsp')");
-                               run("chtype -set $mul t:$__soft_mul","  (skip if '-nodsp')");
+                               run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
+                               run("xilinx_dsp");
+                               run("chtype -set $mul t:$__soft_mul");
                        }
                }
 
@@ -429,7 +436,7 @@ struct SynthXilinxPass : public ScriptPass
                }
 
                if (check_label("map_cells")) {
-                       std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
+                       std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
                        if (widemux > 0)
                                techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
                        run("techmap " + techmap_args);
@@ -437,11 +444,9 @@ struct SynthXilinxPass : public ScriptPass
                }
 
                if (check_label("map_ffs")) {
-                               if (abc9 || help_mode) {
-                                               run("techmap -map +/xilinx/ff_map.v", "('-abc9' only)");
-                                               run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-                                                                               "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT", "('-abc9' only)");
-                               }
+                       if (abc9 || help_mode) {
+                               run("techmap -map " + ff_map_file, "('-abc9' only)");
+                       }
                }
 
                if (check_label("map_luts")) {
@@ -449,10 +454,12 @@ struct SynthXilinxPass : public ScriptPass
                        if (flatten_before_abc)
                                run("flatten");
                        if (help_mode)
-                               run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut', option for '-retime')");
+                               run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')");
                        else if (abc9) {
                                if (family != "xc7")
                                        log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
+                               run("techmap -map +/xilinx/abc_map.v -max_iter 1");
+                               run("read_verilog -icells -lib +/xilinx/abc_model.v");
                                if (nowidelut)
                                        run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
                                else
@@ -470,16 +477,14 @@ struct SynthXilinxPass : public ScriptPass
                        //   has performed any necessary retiming
                        if (!nosrl || help_mode)
                                run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
-
                        std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
                        if (help_mode)
-                                       techmap_args += " [-map +/xilinx/ff_map.v]";
-                       else if (!abc9)
-                                       techmap_args += " -map +/xilinx/ff_map.v";
+                               techmap_args += " [-map " + ff_map_file + "]";
+                       else if (abc9)
+                               techmap_args += " -map +/xilinx/abc_unmap.v";
+                       else
+                               techmap_args += " -map " + ff_map_file;
                        run("techmap " + techmap_args);
-                       if (!abc9)
-                               run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-                                               "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT", "(without '-abc9' only)");
                        run("clean");
                }