xilinx: Test our DSP48A/DSP48A1 simulation models.

[yosys.git] / techlibs / xilinx / tests / test_dsp_model.sh

diff --git a/techlibs/xilinx/tests/test_dsp_model.sh b/techlibs/xilinx/tests/test_dsp_model.sh
index ae925c402186857e434a3a64823c9520e7a7c121..d005cd40c7398b0a55ebdf681f11f5e922a1472d 100644 (file)
--- a/techlibs/xilinx/tests/test_dsp_model.sh
+++ b/techlibs/xilinx/tests/test_dsp_model.sh
@@ -1,14 +1,17 @@
 #!/bin/bash
 set -ex
+if [ -z $VIVADO_DIR ]; then
+       VIVADO_DIR=/opt/Xilinx/Vivado/2019.1
+fi
 sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
 if [ ! -f "test_dsp_model_ref.v" ]; then
-       cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v
+       cp $VIVADO_DIR/data/verilog/src/unisims/DSP48E1.v test_dsp_model_ref.v
 fi
 for tb in macc_overflow_underflow \
-    simd24_preadd_noreg_nocasc simd12_preadd_noreg_nocasc \
-    mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc  \
+       simd24_preadd_noreg_nocasc simd12_preadd_noreg_nocasc \
+        mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc  \
        mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc mult_inreg_preadd_nocasc
 do
-       iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v
+       iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v $VIVADO_DIR/data/verilog/src/glbl.v
        vvp -N ./test_dsp_model
 done