Add force_downto and force_upto wire attributes.

[yosys.git] / techlibs / xilinx / xc3sda_dsp_map.v

diff --git a/techlibs/xilinx/xc3sda_dsp_map.v b/techlibs/xilinx/xc3sda_dsp_map.v
index 87348a1737c7551c9a7ec36b67097f6d11a6c153..258f903955aeb9dcc5fc626f214078c9ba409a96 100644 (file)
--- a/techlibs/xilinx/xc3sda_dsp_map.v
+++ b/techlibs/xilinx/xc3sda_dsp_map.v
@@ -27,7 +27,7 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
                .D(18'b0),
                .P(P_48),
 
-               .OPMODE(8'b0000010)
+               .OPMODE(8'b0000001)
        );
        assign Y = P_48;
 endmodule