tests: Always specify memory mode in every test system.

[gem5.git] / tests / configs / inorder-timing.py

diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index ddf37b5ec093f618236b71bcdc3a2828c46b859b..a92c61ba19cd1af9f0ca190c23abca45f61965ca 100644 (file)
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -29,28 +29,23 @@
 import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
-
-class MyCache(BaseCache):
-    assoc = 2
-    block_size = 64
-    latency = '1ns'
-    mshrs = 10
-    tgts_per_mshr = 5
-
-class MyL1Cache(MyCache):
-    is_top_level = True
+from Caches import *
 
 cpu = InOrderCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
-                              MyL1Cache(size = '256kB'),
-                              MyCache(size = '2MB', latency='10ns'))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
+                              L1Cache(size = '256kB'),
+                              L2Cache(size = '2MB'))
 
 cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
-                physmem = PhysicalMemory(),
-                membus = Bus())
-system.physmem.port = system.membus.port
+                physmem = SimpleDRAM(),
+                membus = CoherentBus(),
+                mem_mode = "timing")
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
+# create the interrupt controller
+cpu.createInterruptController()
 cpu.connectAllPorts(system.membus)
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)