riscv: fix AMO, LR and SC instructions

[gem5.git] / tests / configs / memtest-filter.py

diff --git a/tests/configs/memtest-filter.py b/tests/configs/memtest-filter.py
index 4de009d76beff1338bcb5b6429c59b1b547d43cd..90ad0421c5affe2593320074d9af0d06049094cf 100644 (file)
--- a/tests/configs/memtest-filter.py
+++ b/tests/configs/memtest-filter.py
@@ -28,18 +28,17 @@
 
 import m5
 from m5.objects import *
-m5.util.addToPath('../configs/common')
-from Caches import *
+m5.util.addToPath('../configs/')
+from common.Caches import *
 
 #MAX CORES IS 8 with the fals sharing method
 nb_cores = 8
 cpus = [ MemTest() for i in xrange(nb_cores) ]
 
 # system simulated
-system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
-                funcbus = NoncoherentBus(),
+system = System(cpu = cpus,
                 physmem = SimpleMemory(),
-                membus = CoherentBus(width=16, snoop_filter = SnoopFilter()))
+                membus = SystemXBar(width=16, snoop_filter = SnoopFilter()))
 # Dummy voltage domain for all our clock domains
 system.voltage_domain = VoltageDomain()
 system.clk_domain = SrcClockDomain(clock = '1GHz',
@@ -50,8 +49,8 @@ system.clk_domain = SrcClockDomain(clock = '1GHz',
 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
                                        voltage_domain = system.voltage_domain)
 
-system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16,
-                             snoop_filter = SnoopFilter())
+system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain,
+                        snoop_filter = SnoopFilter())
 system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 
@@ -63,15 +62,11 @@ for cpu in cpus:
     # All cpus are associated with cpu_clk_domain
     cpu.clk_domain = system.cpu_clk_domain
     cpu.l1c = L1Cache(size = '32kB', assoc = 4)
-    cpu.l1c.cpu_side = cpu.test
+    cpu.l1c.cpu_side = cpu.port
     cpu.l1c.mem_side = system.toL2Bus.slave
-    system.funcbus.slave = cpu.functional
 
 system.system_port = system.membus.slave
 
-# connect reference memory to funcbus
-system.funcmem.port = system.funcbus.master
-
 # connect memory to membus
 system.physmem.port = system.membus.master
 
@@ -82,6 +77,3 @@ system.physmem.port = system.membus.master
 
 root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
-#root.trace.flags="Cache CachePort MemoryAccess"
-#root.trace.cycle=1
-