mem: Rename Bus to XBar to better reflect its behaviour

[gem5.git] / tests / configs / memtest-ruby.py

diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 49f1520179e068897e7179da74a020b4c97e8118..08b73cd2fd4aa025274d75879dcd99f48e889330 100644 (file)
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -33,27 +33,23 @@ from m5.defines import buildEnv
 from m5.util import addToPath
 import os, optparse, sys
 
-if buildEnv['FULL_SYSTEM']:
-    panic("This script requires system-emulation mode (*_SE).")
-
 # Get paths we might need
 config_path = os.path.dirname(os.path.abspath(__file__))
 config_root = os.path.dirname(config_path)
 m5_root = os.path.dirname(config_root)
 addToPath(config_root+'/configs/common')
 addToPath(config_root+'/configs/ruby')
+addToPath(config_root+'/configs/topologies')
 
 import Ruby
+import Options
 
 parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
 
-#
 # Add the ruby specific and protocol specific options
-#
 Ruby.define_options(parser)
 
-execfile(os.path.join(config_root, "configs/common", "Options.py"))
-
 (options, args) = parser.parse_args()
 
 #
@@ -68,6 +64,7 @@ options.l1d_assoc=2
 options.l1i_assoc=2
 options.l2_assoc=2
 options.l3_assoc=2
+options.ports=32
 
 #MAX CORES IS 8 with the fals sharing method
 nb_cores = 8
@@ -82,20 +79,40 @@ options.num_cpus = nb_cores
  
 # system simulated
 system = System(cpu = cpus,
-                funcmem = PhysicalMemory(),
-                physmem = PhysicalMemory())
+                funcmem = SimpleMemory(in_addr_map = False),
+                physmem = SimpleMemory(null = True),
+                funcbus = NoncoherentXBar())
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain()
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+                                   voltage_domain = system.voltage_domain)
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+                                       voltage_domain = system.voltage_domain)
+
+# All cpus are associated with cpu_clk_domain
+for cpu in cpus:
+    cpu.clk_domain = system.cpu_clk_domain
+
+system.mem_ranges = AddrRange('256MB')
 
 Ruby.create_system(options, system)
 
-assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
+# Create a separate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+                                        voltage_domain = system.voltage_domain)
+
+assert(len(cpus) == len(system.ruby._cpu_ports))
 
-for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
+for (i, ruby_port) in enumerate(system.ruby._cpu_ports):
      #
      # Tie the cpu test and functional ports to the ruby cpu ports and
      # physmem, respectively
      #
-     cpus[i].test = ruby_port.port
-     cpus[i].functional = system.funcmem.port
+     cpus[i].test = ruby_port.slave
+     cpus[i].functional = system.funcbus.slave
      
      #
      # Since the memtester is incredibly bursty, increase the deadlock
@@ -103,17 +120,14 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
      #
      ruby_port.deadlock_threshold = 1000000
 
-     #
-     # Ruby doesn't need the backing image of memory when running with
-     # the tester.
-     #
-     ruby_port.access_phys_mem = False
+# connect reference memory to funcbus
+system.funcmem.port = system.funcbus.master
 
 # -----------------------
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency