style: Strip newline when checking lines

[gem5.git] / tests / configs / memtest-ruby.py

diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index f1bb733dc7bc972922f829a4f58717e7587214ba..221d28b2ed5ac6dbb0721edc157979bcacd1292f 100644 (file)
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -33,27 +33,23 @@ from m5.defines import buildEnv
 from m5.util import addToPath
 import os, optparse, sys
 
-if buildEnv['FULL_SYSTEM']:
-    panic("This script requires system-emulation mode (*_SE).")
-
 # Get paths we might need
 config_path = os.path.dirname(os.path.abspath(__file__))
 config_root = os.path.dirname(config_path)
 m5_root = os.path.dirname(config_root)
 addToPath(config_root+'/configs/common')
 addToPath(config_root+'/configs/ruby')
+addToPath(config_root+'/configs/topologies')
 
 import Ruby
+import Options
 
 parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
 
-#
 # Add the ruby specific and protocol specific options
-#
 Ruby.define_options(parser)
 
-execfile(os.path.join(config_root, "configs/common", "Options.py"))
-
 (options, args) = parser.parse_args()
 
 #
@@ -68,40 +64,63 @@ options.l1d_assoc=2
 options.l1i_assoc=2
 options.l2_assoc=2
 options.l3_assoc=2
+options.ports=32
 
 #MAX CORES IS 8 with the fals sharing method
 nb_cores = 8
 
 # ruby does not support atomic, functional, or uncacheable accesses
-cpus = [ MemTest(atomic=False, percent_functional=0, \
-                 percent_uncacheable=0) \
+cpus = [ MemTest(percent_functional=50,
+                 percent_uncacheable=0, suppress_func_warnings=True) \
          for i in xrange(nb_cores) ]
 
 # overwrite options.num_cpus with the nb_cores value
 options.num_cpus = nb_cores
- 
+
 # system simulated
-system = System(cpu = cpus,
-                funcmem = PhysicalMemory(),
-                physmem = PhysicalMemory())
+system = System(cpu = cpus)
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain()
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+                                   voltage_domain = system.voltage_domain)
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+                                       voltage_domain = system.voltage_domain)
 
-system.ruby = Ruby.create_system(options, system)
+# All cpus are associated with cpu_clk_domain
+for cpu in cpus:
+    cpu.clk_domain = system.cpu_clk_domain
 
-assert(len(cpus) == len(system.ruby.cpu_ruby_ports))
+system.mem_ranges = AddrRange('256MB')
 
-for (i, ruby_port) in enumerate(system.ruby.cpu_ruby_ports):
+Ruby.create_system(options, False, system)
+
+# Create a separate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+                                        voltage_domain = system.voltage_domain)
+
+assert(len(cpus) == len(system.ruby._cpu_ports))
+
+for (i, ruby_port) in enumerate(system.ruby._cpu_ports):
      #
-     # Tie the cpu test and functional ports to the ruby cpu ports and
+     # Tie the cpu port to the ruby cpu ports and
      # physmem, respectively
      #
-     cpus[i].test = ruby_port.port
-     cpus[i].functional = system.funcmem.port
+     cpus[i].port = ruby_port.slave
+
+     #
+     # Since the memtester is incredibly bursty, increase the deadlock
+     # threshold to 1 million cycles
+     #
+     ruby_port.deadlock_threshold = 1000000
 
 # -----------------------
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency