mem: Allow read-only caches and check compliance

[gem5.git] / tests / configs / memtest.py

diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 55c086d69ebc87498c40bb05bfec7420f8dd12d7..5bbfeb774bb27121804f0b8361a8129bf74ca0d3 100644 (file)
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -33,17 +33,24 @@ from Caches import *
 
 #MAX CORES IS 8 with the fals sharing method
 nb_cores = 8
-cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ]
+cpus = [ MemTest() for i in xrange(nb_cores) ]
 
 # system simulated
-system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
-                funcbus = NoncoherentBus(),
+system = System(cpu = cpus,
                 physmem = SimpleMemory(),
-                membus = CoherentBus(clock="1GHz", width=16))
+                membus = SystemXBar())
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain()
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+                                   voltage_domain = system.voltage_domain)
 
-# l2cache & bus
-system.toL2Bus = CoherentBus(clock="2GHz", width=16)
-system.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8)
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+                                       voltage_domain = system.voltage_domain)
+
+system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain)
+system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 
 # connect l2c to membus
@@ -51,16 +58,14 @@ system.l2c.mem_side = system.membus.slave
 
 # add L1 caches
 for cpu in cpus:
+    # All cpus are associated with cpu_clk_domain
+    cpu.clk_domain = system.cpu_clk_domain
     cpu.l1c = L1Cache(size = '32kB', assoc = 4)
-    cpu.l1c.cpu_side = cpu.test
+    cpu.l1c.cpu_side = cpu.port
     cpu.l1c.mem_side = system.toL2Bus.slave
-    system.funcbus.slave = cpu.functional
 
 system.system_port = system.membus.slave
 
-# connect reference memory to funcbus
-system.funcmem.port = system.funcbus.master
-
 # connect memory to membus
 system.physmem.port = system.membus.master
 
@@ -71,6 +76,4 @@ system.physmem.port = system.membus.master
 
 root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
-#root.trace.flags="Cache CachePort MemoryAccess"
-#root.trace.cycle=1