mem: Allow read-only caches and check compliance

[gem5.git] / tests / configs / memtest.py

diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 93ea4cc0ec9485c85104d749dc2d7484ac29c156..5bbfeb774bb27121804f0b8361a8129bf74ca0d3 100644 (file)
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -28,62 +28,52 @@
 
 import m5
 from m5.objects import *
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    latency = '1ns'
-    block_size = 64
-    mshrs = 12
-    tgts_per_mshr = 8
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    latency = '10ns'
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
+m5.util.addToPath('../configs/common')
+from Caches import *
 
 #MAX CORES IS 8 with the fals sharing method
 nb_cores = 8
 cpus = [ MemTest() for i in xrange(nb_cores) ]
 
 # system simulated
-system = System(cpu = cpus, funcmem = PhysicalMemory(),
-                physmem = PhysicalMemory(),
-                membus = Bus(clock="500GHz", width=16))
+system = System(cpu = cpus,
+                physmem = SimpleMemory(),
+                membus = SystemXBar())
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain()
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+                                   voltage_domain = system.voltage_domain)
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+                                       voltage_domain = system.voltage_domain)
 
-# l2cache & bus
-system.toL2Bus = Bus(clock="500GHz", width=16)
-system.l2c = L2(size='64kB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
+system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain)
+system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
 
 # connect l2c to membus
-system.l2c.mem_side = system.membus.port
+system.l2c.mem_side = system.membus.slave
 
 # add L1 caches
 for cpu in cpus:
-    cpu.l1c = L1(size = '32kB', assoc = 4)
-    cpu.l1c.cpu_side = cpu.test
-    cpu.l1c.mem_side = system.toL2Bus.port
-    system.funcmem.port = cpu.functional
+    # All cpus are associated with cpu_clk_domain
+    cpu.clk_domain = system.cpu_clk_domain
+    cpu.l1c = L1Cache(size = '32kB', assoc = 4)
+    cpu.l1c.cpu_side = cpu.port
+    cpu.l1c.mem_side = system.toL2Bus.slave
+
+system.system_port = system.membus.slave
 
 # connect memory to membus
-system.physmem.port = system.membus.port
+system.physmem.port = system.membus.master
 
 
 # -----------------------
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
-#root.trace.flags="Cache CachePort MemoryAccess"
-#root.trace.cycle=1