MEM: Introduce the master/slave port roles in the Python classes

[gem5.git] / tests / configs / memtest.py

diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 6fe244acfb5528b5bb1d8fce36414bfe0ddd55be..6fface748bb99949e8beb639ff4fad94a3147ad2 100644 (file)
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -38,7 +38,7 @@ class L1(BaseCache):
     block_size = 64
     mshrs = 12
     tgts_per_mshr = 8
-    protocol = CoherenceProtocol(protocol='moesi')
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -63,27 +63,29 @@ system = System(cpu = cpus, funcmem = PhysicalMemory(),
 # l2cache & bus
 system.toL2Bus = Bus(clock="500GHz", width=16)
 system.l2c = L2(size='64kB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.cpu_side = system.toL2Bus.master
 
 # connect l2c to membus
-system.l2c.mem_side = system.membus.port
+system.l2c.mem_side = system.membus.slave
 
 # add L1 caches
 for cpu in cpus:
     cpu.l1c = L1(size = '32kB', assoc = 4)
     cpu.l1c.cpu_side = cpu.test
-    cpu.l1c.mem_side = system.toL2Bus.port
+    cpu.l1c.mem_side = system.toL2Bus.slave
     system.funcmem.port = cpu.functional
 
+system.system_port = system.membus.slave
+
 # connect memory to membus
-system.physmem.port = system.membus.port
+system.physmem.port = system.membus.master
 
 
 # -----------------------
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 #root.trace.flags="Cache CachePort MemoryAccess"
 #root.trace.cycle=1