Merge zizzer:/bk/newmem

[gem5.git] / tests / configs / memtest.py

diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 17992976cb3cab87dd365965bca82a26e62d139f..f56edef4a1e09793bb4e937da3bfbe8152ce4de4 100644 (file)
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -53,14 +53,14 @@ class L2(BaseCache):
 
 #MAX CORES IS 8 with the fals sharing method
 nb_cores = 8
-cpus = [ MemTest(max_loads=1e12, percent_uncacheable=0) for i in xrange(nb_cores) ]
+cpus = [ MemTest() for i in xrange(nb_cores) ]
 
 # system simulated
 system = System(cpu = cpus, funcmem = PhysicalMemory(),
-                physmem = PhysicalMemory(), membus = Bus())
+                physmem = PhysicalMemory(), membus = Bus(clock="500GHz", width=16))
 
 # l2cache & bus
-system.toL2Bus = Bus()
+system.toL2Bus = Bus(clock="500GHz", width=16)
 system.l2c = L2(size='64kB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.port
 
@@ -90,4 +90,6 @@ system.physmem.port = system.membus.port
 
 root = Root( system = system )
 root.system.mem_mode = 'timing'
-root.trace.flags="Cache"
+#root.trace.flags="Cache CachePort MemoryAccess"
+#root.trace.cycle=1
+