sparc: update long regressions

[gem5.git] / tests / configs / memtest.py

diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 116e71af64afda1a44d5510a11e94a7633b19a5f..f6238147391640f8754a6cd1a7eef8831af31e1e 100644 (file)
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -34,11 +34,11 @@ from m5.objects import *
 # ====================
 
 class L1(BaseCache):
-    latency = 1
+    latency = '1ns'
     block_size = 64
     mshrs = 12
     tgts_per_mshr = 8
-    protocol = CoherenceProtocol(protocol='moesi')
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -46,39 +46,35 @@ class L1(BaseCache):
 
 class L2(BaseCache):
     block_size = 64
-    latency = 10
+    latency = '10ns'
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
 
 #MAX CORES IS 8 with the fals sharing method
 nb_cores = 8
-cpus = [ MemTest(max_loads=1e12, percent_uncacheable=0, progress_interval=1000) for i in xrange(nb_cores) ]
+cpus = [ MemTest() for i in xrange(nb_cores) ]
 
 # system simulated
 system = System(cpu = cpus, funcmem = PhysicalMemory(),
-                physmem = PhysicalMemory(), membus = Bus(clock="500GHz", width=16))
+                physmem = PhysicalMemory(),
+                membus = Bus(clock="500GHz", width=16))
 
 # l2cache & bus
 system.toL2Bus = Bus(clock="500GHz", width=16)
 system.l2c = L2(size='64kB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.num_cpus = nb_cores
 
 # connect l2c to membus
 system.l2c.mem_side = system.membus.port
 
-which_port = 0
 # add L1 caches
 for cpu in cpus:
     cpu.l1c = L1(size = '32kB', assoc = 4)
     cpu.l1c.cpu_side = cpu.test
     cpu.l1c.mem_side = system.toL2Bus.port
-    if  which_port == 0:
-         system.funcmem.port = cpu.functional
-         which_port = 1
-    else:
-         system.funcmem.functional = cpu.functional
-
+    system.funcmem.port = cpu.functional
 
 # connect memory to membus
 system.physmem.port = system.membus.port
@@ -90,6 +86,6 @@ system.physmem.port = system.membus.port
 
 root = Root( system = system )
 root.system.mem_mode = 'timing'
-#root.trace.flags="Cache CachePort Bus"
-#root.trace.cycle=3810800
+#root.trace.flags="Cache CachePort MemoryAccess"
+#root.trace.cycle=1