sparc: update long regressions

[gem5.git] / tests / configs / memtest.py

diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index cfcefbcb9f7849e82f62b201160453b8f8bcc5a7..f6238147391640f8754a6cd1a7eef8831af31e1e 100644 (file)
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -34,11 +34,11 @@ from m5.objects import *
 # ====================
 
 class L1(BaseCache):
-    latency = 1
+    latency = '1ns'
     block_size = 64
-    mshrs = 4
+    mshrs = 12
     tgts_per_mshr = 8
-    protocol = CoherenceProtocol(protocol='moesi')
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -46,22 +46,25 @@ class L1(BaseCache):
 
 class L2(BaseCache):
     block_size = 64
-    latency = 100
+    latency = '10ns'
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
 
-nb_cores = 1
-cpus = [ MemTest(max_loads=1e12) for i in xrange(nb_cores) ]
+#MAX CORES IS 8 with the fals sharing method
+nb_cores = 8
+cpus = [ MemTest() for i in xrange(nb_cores) ]
 
 # system simulated
 system = System(cpu = cpus, funcmem = PhysicalMemory(),
-                physmem = PhysicalMemory(), membus = Bus())
+                physmem = PhysicalMemory(),
+                membus = Bus(clock="500GHz", width=16))
 
 # l2cache & bus
-system.toL2Bus = Bus()
-system.l2c = L2(size='4MB', assoc=8)
+system.toL2Bus = Bus(clock="500GHz", width=16)
+system.l2c = L2(size='64kB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.num_cpus = nb_cores
 
 # connect l2c to membus
 system.l2c.mem_side = system.membus.port
@@ -73,7 +76,6 @@ for cpu in cpus:
     cpu.l1c.mem_side = system.toL2Bus.port
     system.funcmem.port = cpu.functional
 
-
 # connect memory to membus
 system.physmem.port = system.membus.port
 
@@ -84,5 +86,6 @@ system.physmem.port = system.membus.port
 
 root = Root( system = system )
 root.system.mem_mode = 'timing'
-#root.trace.flags="InstExec"
-root.trace.flags="Bus"
+#root.trace.flags="Cache CachePort MemoryAccess"
+#root.trace.cycle=1
+