mem: Rename Bus to XBar to better reflect its behaviour

[gem5.git] / tests / configs / o3-timing-mp-ruby.py

diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index 2f8829db0dd80d883cede28e42c482c57f4a3164..3fea4ed7117861379fd8b502044c13547c54e060 100644 (file)
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -29,6 +29,7 @@
 import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
+m5.util.addToPath('../configs/topologies')
 
 nb_cores = 4
 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
@@ -37,15 +38,26 @@ import ruby_config
 ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
 
 # system simulated
-system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
+system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentXBar(),
+                mem_mode = "timing",
+                clk_domain = SrcClockDomain(clock = '1GHz'))
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
 
 for cpu in cpus:
+    # create the interrupt controller
+    cpu.createInterruptController()
     cpu.connectAllPorts(system.membus)
-    cpu.clock = '2GHz'
+    # All cpus are associated with cpu_clk_domain
+    cpu.clk_domain = system.cpu_clk_domain
 
 # connect memory to membus
-system.physmem.port = system.membus.port
+system.physmem.port = system.membus.master
 
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.slave
 
 # -----------------------
 # run simulation