# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Ron Dreslinski
import m5
from m5.objects import *
-m5.AddToPath('../configs/common')
nb_cores = 4
-cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
+cpus = [ DerivO3CPU(cpu_id=i) for i in range(nb_cores) ]
import ruby_config
-ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores)
+ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
# system simulated
-system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
+system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(),
+ mem_mode = "timing",
+ clk_domain = SrcClockDomain(clock = '1GHz'))
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
for cpu in cpus:
- cpu.connectMemPorts(system.membus)
- cpu.clock = '2GHz'
+ # create the interrupt controller
+ cpu.createInterruptController()
+ cpu.connectAllPorts(system.membus)
+ # All cpus are associated with cpu_clk_domain
+ cpu.clk_domain = system.cpu_clk_domain
# connect memory to membus
-system.physmem.port = system.membus.port
+system.physmem.port = system.membus.master
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.slave
# -----------------------
# run simulation
# -----------------------
-root = Root(system = system)
+root = Root(full_system = False, system = system)
root.system.mem_mode = 'timing'