sim: Use the old work item behavior by default

[gem5.git] / tests / configs / o3-timing-mp-ruby.py

diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index b9aade84e7632d6d3e3588fd8b022b1418e3f002..fb2d56fd1f5e789fc82327269cd8805c00eb89a2 100644 (file)
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -28,26 +28,40 @@
 
 import m5
 from m5.objects import *
-m5.AddToPath('../configs/common')
+m5.util.addToPath('../configs/common')
+m5.util.addToPath('../configs/topologies')
 
 nb_cores = 4
 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
 
+import ruby_config
+ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
+
 # system simulated
-system = System(cpu = cpus, physmem = RubyMemory(num_cpus=nb_cores),
-                membus = Bus())
+system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(),
+                mem_mode = "timing",
+                clk_domain = SrcClockDomain(clock = '1GHz'))
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
 
 for cpu in cpus:
-    cpu.connectMemPorts(system.membus)
-    cpu.clock = '2GHz'
+    # create the interrupt controller
+    cpu.createInterruptController()
+    cpu.connectAllPorts(system.membus)
+    # All cpus are associated with cpu_clk_domain
+    cpu.clk_domain = system.cpu_clk_domain
 
 # connect memory to membus
-system.physmem.port = system.membus.port
+system.physmem.port = system.membus.master
 
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.slave
 
 # -----------------------
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'