mem: Allow read-only caches and check compliance

[gem5.git] / tests / configs / o3-timing-ruby.py

diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py
index b967a508043f099e5ec0749988e2b656a1efdcee..c47d9f355caa3de7575397aaf692cca1369485db 100644 (file)
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -29,18 +29,30 @@
 import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
+m5.util.addToPath('../configs/topologies')
 
 
 import ruby_config
 ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)
 
 cpu = DerivO3CPU(cpu_id=0)
-cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
                 physmem = ruby_memory,
-                membus = Bus())
-system.physmem.port = system.membus.port
+                membus = SystemXBar(),
+                mem_mode = "timing",
+                clk_domain = SrcClockDomain(clock = '1GHz'))
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
+
+system.physmem.port = system.membus.master
+# create the interrupt controller
+cpu.createInterruptController()
 cpu.connectAllPorts(system.membus)
 
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.slave
+
 root = Root(full_system = False, system = system)