config: Unify caches used in regressions and adjust L2 MSHRs

[gem5.git] / tests / configs / o3-timing.py

diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 227e1ba2111ef4a6d0e024e74d3d1fc16408f4cb..30c2f413eca988aaad5b41b531fd1fc212f38f30 100644 (file)
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -28,25 +28,25 @@
 
 import m5
 from m5.objects import *
-m5.AddToPath('../configs/common')
-from FullO3Config import *
+m5.util.addToPath('../configs/common')
+from Caches import *
 
-class MyCache(BaseCache):
-    assoc = 2
-    block_size = 64
-    latency = 1
-    mshrs = 10
-    tgts_per_mshr = 5
-
-cpu = DetailedO3CPU()
-cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
-                              MyCache(size = '2MB'))
-cpu.mem = cpu.dcache
+cpu = DerivO3CPU(cpu_id=0)
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
+                              L1Cache(size = '256kB'),
+                              L2Cache(size = '2MB'))
+# @todo Note that the L2 latency here is unmodified and 2 cycles,
+# should set hit latency and response latency to 20 cycles as for
+# other scripts
+cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
-                physmem = PhysicalMemory(),
-                membus = Bus())
-system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+                physmem = SimpleDRAM(),
+                membus = CoherentBus())
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
+# create the interrupt controller
+cpu.createInterruptController()
+cpu.connectAllPorts(system.membus)
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)