system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
for i in xrange(options.num_cpus)]
-Ruby.create_system(options, system, system.piobus, system._dma_ports)
+Ruby.create_system(options, True, system, system.iobus, system._dma_ports)
# Create a seperate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
+# Connect the ruby io port to the PIO bus,
+# assuming that there is just one such port.
+system.iobus.master = system.ruby._io_port.slave
+
for (i, cpu) in enumerate(system.cpu):
# create the interrupt controller
cpu.createInterruptController()
# Tie the cpu ports to the correct ruby system ports
- cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
- cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
- cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
- cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
- cpu.interrupts.pio = system.ruby._cpu_ruby_ports[i].master
- cpu.interrupts.int_master = system.ruby._cpu_ruby_ports[i].slave
- cpu.interrupts.int_slave = system.ruby._cpu_ruby_ports[i].master
-
- # Set access_phys_mem to True for ruby port
- system.ruby._cpu_ruby_ports[i].access_phys_mem = True
+ cpu.icache_port = system.ruby._cpu_ports[i].slave
+ cpu.dcache_port = system.ruby._cpu_ports[i].slave
+ cpu.itb.walker.port = system.ruby._cpu_ports[i].slave
+ cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave
-system.physmem = [DDR3_1600_x64(range = r)
- for r in system.mem_ranges]
-for i in xrange(len(system.physmem)):
- system.physmem[i].port = system.piobus.master
+ cpu.interrupts[0].pio = system.ruby._cpu_ports[i].master
+ cpu.interrupts[0].int_master = system.ruby._cpu_ports[i].slave
+ cpu.interrupts[0].int_slave = system.ruby._cpu_ports[i].master
root = Root(full_system = True, system = system)
m5.ticks.setGlobalFrequency('1THz')