tests: Fail checkpoint regressions if no cpt has been taken

[gem5.git] / tests / configs / realview-simple-timing-dual.py

diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py
index 5b8e6e0e3da503ae9571a2d6d67b9f6e341c8d5e..7f3d384ff1a1f6e43c21dd4bad0bc72af3f40059 100644 (file)
--- a/tests/configs/realview-simple-timing-dual.py
+++ b/tests/configs/realview-simple-timing-dual.py
@@ -1,6 +1,15 @@
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2012, 2019 ARM Limited
 # All rights reserved.
 #
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
 # met: redistributions of source code must retain the above copyright
@@ -23,44 +32,12 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt
 
-import m5
 from m5.objects import *
-m5.util.addToPath('../configs/common')
-import FSConfig
-from Benchmarks import *
-from Caches import *
-
-#cpu
-cpus = [TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
-#the system
-system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
-system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
-system.iocache.cpu_side = system.iobus.master
-system.iocache.mem_side = system.membus.slave
-
-system.cpu = cpus
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus(clock = '2GHz')
-
-#connect up the l2 cache
-system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
-
-#connect up the cpu and l1s
-for c in cpus:
-    c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
-                              L1Cache(size = '32kB', assoc = 4))
-    # create the interrupt controller
-    c.createInterruptController()
-    # connect cpu level-1 caches to shared level-2 cache
-    c.connectAllPorts(system.toL2Bus, system.membus)
-    c.clock = '2GHz'
-
-
-root = Root(full_system=True, system=system)
-m5.ticks.setGlobalFrequency('1THz')
+from arm_generic import *
 
+root = LinuxArmFSSystem(aarch64_kernel=False,
+                        mem_mode='timing',
+                        mem_class=DDR3_1600_8x8,
+                        cpu_class=TimingSimpleCPU,
+                        num_cpus=2).create_root()