mem: Allow read-only caches and check compliance

[gem5.git] / tests / configs / rubytest-ruby.py

diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index 5bdfe39ddf24ead7c000c21710f9cda9fe0087cd..22334efb4cd18a5471285f526b36da58854baa88 100644 (file)
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -34,47 +34,68 @@ from m5.defines import buildEnv
 from m5.util import addToPath
 import os, optparse, sys
 
-if buildEnv['FULL_SYSTEM']:
-    panic("This script requires system-emulation mode (*_SE).")
-
 # Get paths we might need.  It's expected this file is in m5/configs/example.
 config_path = os.path.dirname(os.path.abspath(__file__))
 config_root = os.path.dirname(config_path)
 m5_root = os.path.dirname(config_root)
 addToPath(config_root+'/configs/common')
 addToPath(config_root+'/configs/ruby')
-addToPath(config_root+'/configs/ruby/protocols')
-addToPath(config_root+'/configs/ruby/topologies')
+addToPath(config_root+'/configs/topologies')
 
 import Ruby
+import Options
 
 parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
+
+# Add the ruby specific and protocol specific options
+Ruby.define_options(parser)
+
+(options, args) = parser.parse_args()
 
 #
 # Set the default cache size and associativity to be very small to encourage
 # races between requests and writebacks.
 #
-parser.add_option("--l1d_size", type="string", default="256B")
-parser.add_option("--l1i_size", type="string", default="256B")
-parser.add_option("--l2_size", type="string", default="512B")
-parser.add_option("--l1d_assoc", type="int", default=2)
-parser.add_option("--l1i_assoc", type="int", default=2)
-parser.add_option("--l2_assoc", type="int", default=2)
-
-execfile(os.path.join(config_root, "configs/common", "Options.py"))
-
-(options, args) = parser.parse_args()
+options.l1d_size="256B"
+options.l1i_size="256B"
+options.l2_size="512B"
+options.l3_size="1kB"
+options.l1d_assoc=2
+options.l1i_assoc=2
+options.l2_assoc=2
+options.l3_assoc=2
+options.ports=32
+
+# Turn on flush check for the hammer protocol
+check_flush = False
+if buildEnv['PROTOCOL'] == 'MOESI_hammer':
+    check_flush = True
 
 #
 # create the tester and system, including ruby
 #
-tester = RubyTester(checks_to_complete = 100, wakeup_frequency = 10)
+tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
+                    wakeup_frequency = 10, num_cpus = options.num_cpus)
+
+# We set the testers as cpu for ruby to find the correct clock domains
+# for the L1 Objects.
+system = System(cpu = tester)
+
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+                                   voltage_domain = system.voltage_domain)
+
+system.mem_ranges = AddrRange('256MB')
 
-system = System(physmem = PhysicalMemory())
+Ruby.create_system(options, False, system)
 
-system.ruby = Ruby.create_system(options, system.physmem)
+# Create a separate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = '1GHz',
+                                        voltage_domain = system.voltage_domain)
 
-assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ports))
 
 #
 # The tester is most effective when randomization is turned on and
@@ -82,11 +103,14 @@ assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
 #
 system.ruby.randomization = True
 
-for ruby_port in system.ruby.cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ports:
     #
-    # Tie the ruby tester ports to the ruby cpu ports
+    # Tie the ruby tester ports to the ruby cpu read and write ports
     #
-    tester.cpuPort = ruby_port.port
+    if ruby_port.support_data_reqs:
+         tester.cpuDataPort = ruby_port.slave
+    if ruby_port.support_inst_reqs:
+         tester.cpuInstPort = ruby_port.slave
 
     #
     # Tell the sequencer this is the ruby tester so that it
@@ -98,7 +122,7 @@ for ruby_port in system.ruby.cpu_ruby_ports:
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root(full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency