mem: Allow read-only caches and check compliance

[gem5.git] / tests / configs / rubytest-ruby.py

diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index 7bb7b90145b1adf7804d9e75d13813f4f15a6dc8..22334efb4cd18a5471285f526b36da58854baa88 100644 (file)
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -40,6 +40,7 @@ config_root = os.path.dirname(config_path)
 m5_root = os.path.dirname(config_root)
 addToPath(config_root+'/configs/common')
 addToPath(config_root+'/configs/ruby')
+addToPath(config_root+'/configs/topologies')
 
 import Ruby
 import Options
@@ -64,17 +65,37 @@ options.l1d_assoc=2
 options.l1i_assoc=2
 options.l2_assoc=2
 options.l3_assoc=2
+options.ports=32
+
+# Turn on flush check for the hammer protocol
+check_flush = False
+if buildEnv['PROTOCOL'] == 'MOESI_hammer':
+    check_flush = True
 
 #
 # create the tester and system, including ruby
 #
-tester = RubyTester(checks_to_complete = 100, wakeup_frequency = 10)
+tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
+                    wakeup_frequency = 10, num_cpus = options.num_cpus)
+
+# We set the testers as cpu for ruby to find the correct clock domains
+# for the L1 Objects.
+system = System(cpu = tester)
+
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+                                   voltage_domain = system.voltage_domain)
+
+system.mem_ranges = AddrRange('256MB')
 
-system = System(tester = tester, physmem = SimpleMemory())
+Ruby.create_system(options, False, system)
 
-Ruby.create_system(options, system)
+# Create a separate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = '1GHz',
+                                        voltage_domain = system.voltage_domain)
 
-assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ports))
 
 #
 # The tester is most effective when randomization is turned on and
@@ -82,11 +103,14 @@ assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
 #
 system.ruby.randomization = True
 
-for ruby_port in system.ruby._cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ports:
     #
-    # Tie the ruby tester ports to the ruby cpu ports
+    # Tie the ruby tester ports to the ruby cpu read and write ports
     #
-    tester.cpuPort = ruby_port.slave
+    if ruby_port.support_data_reqs:
+         tester.cpuDataPort = ruby_port.slave
+    if ruby_port.support_inst_reqs:
+         tester.cpuInstPort = ruby_port.slave
 
     #
     # Tell the sequencer this is the ruby tester so that it
@@ -94,12 +118,6 @@ for ruby_port in system.ruby._cpu_ruby_ports:
     #
     ruby_port.using_ruby_tester = True
 
-    #
-    # Ruby doesn't need the backing image of memory when running with
-    # the tester.
-    #
-    ruby_port.access_phys_mem = False
-
 # -----------------------
 # run simulation
 # -----------------------