sparc: update long regressions

[gem5.git] / tests / configs / simple-atomic-mp.py

diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index cc1a36dda8d2916ec8221c605226123e8c0a12b1..4db741b8ac0048b0a606c56268b39fb8d6881279 100644 (file)
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -34,11 +34,11 @@ from m5.objects import *
 # ====================
 
 class L1(BaseCache):
-    latency = 1
+    latency = '1ns'
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
-    protocol = CoherenceProtocol(protocol='moesi')
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -46,22 +46,23 @@ class L1(BaseCache):
 
 class L2(BaseCache):
     block_size = 64
-    latency = 100
+    latency = '10ns'
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
 
 nb_cores = 4
-cpus = [ AtomicSimpleCPU() for i in xrange(nb_cores) ]
+cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
 
 # system simulated
-system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
+system = System(cpu = cpus, physmem = PhysicalMemory(range = AddrRange('1024MB')), membus =
 Bus())
 
 # l2cache & bus
 system.toL2Bus = Bus()
 system.l2c = L2(size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.num_cpus = nb_cores
 
 # connect l2c to membus
 system.l2c.mem_side = system.membus.port
@@ -70,9 +71,9 @@ system.l2c.mem_side = system.membus.port
 for cpu in cpus:
     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
-    cpu.mem = cpu.dcache
     # connect cpu level-1 caches to shared level-2 cache
-    cpu.connectMemPorts(system.toL2Bus)
+    cpu.connectAllPorts(system.toL2Bus, system.membus)
+    cpu.clock = '2GHz'
 
 # connect memory to membus
 system.physmem.port = system.membus.port