-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
membus = Bus())
system.physmem.port = system.membus.port
system.cpu.connectMemPorts(system.membus)
-system.cpu.mem = system.physmem
+system.cpu.clock = '2GHz'
root = Root(system = system)