style: Strip newline when checking lines

[gem5.git] / tests / configs / simple-timing-mp-ruby.py

diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index 58ca862e18a202fc914bb619d5c8e30f22efe83e..263b330fb10345299d7c8ed1ba96932e58b63488 100644 (file)
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -32,27 +32,23 @@ from m5.defines import buildEnv
 from m5.util import addToPath
 import os, optparse, sys
 
-if buildEnv['FULL_SYSTEM']:
-    panic("This script requires system-emulation mode (*_SE).")
-
 # Get paths we might need
 config_path = os.path.dirname(os.path.abspath(__file__))
 config_root = os.path.dirname(config_path)
 m5_root = os.path.dirname(config_root)
 addToPath(config_root+'/configs/common')
 addToPath(config_root+'/configs/ruby')
+addToPath(config_root+'/configs/topologies')
 
+import Options
 import Ruby
 
 parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
 
-#
 # Add the ruby specific and protocol specific options
-#
 Ruby.define_options(parser)
 
-execfile(os.path.join(config_root, "configs/common", "Options.py"))
-
 (options, args) = parser.parse_args()
 
 #
@@ -75,27 +71,33 @@ cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
 options.num_cpus = nb_cores
 
 # system simulated
-system = System(cpu = cpus, physmem = PhysicalMemory())
+system = System(cpu = cpus, clk_domain = SrcClockDomain(clock = '1GHz'))
 
-Ruby.create_system(options, system)
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
 
-assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+Ruby.create_system(options, False, system)
+
+# Create a separate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
+assert(options.num_cpus == len(system.ruby._cpu_ports))
 
 for (i, cpu) in enumerate(system.cpu):
+    # create the interrupt controller
+    cpu.createInterruptController()
+
     #
     # Tie the cpu ports to the ruby cpu ports
     #
-    cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
-    cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
-
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
+    cpu.connectAllPorts(system.ruby._cpu_ports[i])
 
 # -----------------------
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system=False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency