from m5.util import addToPath
import os, optparse, sys
-if buildEnv['FULL_SYSTEM']:
- panic("This script requires system-emulation mode (*_SE).")
-
# Get paths we might need
config_path = os.path.dirname(os.path.abspath(__file__))
config_root = os.path.dirname(config_path)
m5_root = os.path.dirname(config_root)
addToPath(config_root+'/configs/common')
addToPath(config_root+'/configs/ruby')
+addToPath(config_root+'/configs/topologies')
+import Options
import Ruby
parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
+
+# Add the ruby specific and protocol specific options
+Ruby.define_options(parser)
+
+(options, args) = parser.parse_args()
#
# Set the default cache size and associativity to be very small to encourage
# races between requests and writebacks.
#
-parser.add_option("--l1d_size", type="string", default="256B")
-parser.add_option("--l1i_size", type="string", default="256B")
-parser.add_option("--l2_size", type="string", default="512B")
-parser.add_option("--l1d_assoc", type="int", default=2)
-parser.add_option("--l1i_assoc", type="int", default=2)
-parser.add_option("--l2_assoc", type="int", default=2)
-
-execfile(os.path.join(config_root, "configs/common", "Options.py"))
-
-(options, args) = parser.parse_args()
+options.l1d_size="256B"
+options.l1i_size="256B"
+options.l2_size="512B"
+options.l3_size="1kB"
+options.l1d_assoc=2
+options.l1i_assoc=2
+options.l2_assoc=2
+options.l3_assoc=2
nb_cores = 4
cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
options.num_cpus = nb_cores
# system simulated
-system = System(cpu = cpus,
- physmem = PhysicalMemory())
+system = System(cpu = cpus, clk_domain = SrcClockDomain(clock = '1GHz'))
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
-system.ruby = Ruby.create_system(options, system.physmem)
+Ruby.create_system(options, False, system)
-assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+# Create a separate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
+assert(options.num_cpus == len(system.ruby._cpu_ports))
for (i, cpu) in enumerate(system.cpu):
+ # create the interrupt controller
+ cpu.createInterruptController()
+
#
# Tie the cpu ports to the ruby cpu ports
#
- cpu.icache_port = system.ruby.cpu_ruby_ports[i].port
- cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port
+ cpu.connectAllPorts(system.ruby._cpu_ports[i])
# -----------------------
# run simulation
# -----------------------
-root = Root( system = system )
+root = Root( full_system=False, system = system )
root.system.mem_mode = 'timing'
# Not much point in this being higher than the L1 latency