sparc: update long regressions

[gem5.git] / tests / configs / simple-timing-mp-ruby.py

diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index ed4b5b4c6d9b4115f02e1a54f8390675ac39dc37..56b7ae1eb513914d0d08f96eb5edd122c653f77d 100644 (file)
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -28,24 +28,65 @@
 
 import m5
 from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+import os, optparse, sys
+
+if buildEnv['FULL_SYSTEM']:
+    panic("This script requires system-emulation mode (*_SE).")
+
+# Get paths we might need
+config_path = os.path.dirname(os.path.abspath(__file__))
+config_root = os.path.dirname(config_path)
+m5_root = os.path.dirname(config_root)
+addToPath(config_root+'/configs/common')
+addToPath(config_root+'/configs/ruby')
+
+import Ruby
+
+parser = optparse.OptionParser()
+
+#
+# Add the ruby specific and protocol specific options
+#
+Ruby.define_options(parser)
+
+execfile(os.path.join(config_root, "configs/common", "Options.py"))
+
+(options, args) = parser.parse_args()
+
+#
+# Set the default cache size and associativity to be very small to encourage
+# races between requests and writebacks.
+#
+options.l1d_size="256B"
+options.l1i_size="256B"
+options.l2_size="512B"
+options.l3_size="1kB"
+options.l1d_assoc=2
+options.l1i_assoc=2
+options.l2_assoc=2
+options.l3_assoc=2
 
 nb_cores = 4
 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
 
-import ruby_config
-ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores)
+# overwrite the num_cpus to equal nb_cores
+options.num_cpus = nb_cores
 
 # system simulated
-system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
+system = System(cpu = cpus, physmem = PhysicalMemory())
 
-# add L1 caches
-for cpu in cpus:
-    cpu.connectMemPorts(system.membus)
-    cpu.clock = '2GHz'
+system.ruby = Ruby.create_system(options, system)
 
-# connect memory to membus
-system.physmem.port = system.membus.port
+assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
 
+for (i, cpu) in enumerate(system.cpu):
+    #
+    # Tie the cpu ports to the ruby cpu ports
+    #
+    cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
+    cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
 
 # -----------------------
 # run simulation
@@ -53,3 +94,6 @@ system.physmem.port = system.membus.port
 
 root = Root( system = system )
 root.system.mem_mode = 'timing'
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')