Merge zizzer:/bk/newmem

[gem5.git] / tests / configs / simple-timing-mp.py

diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index 8f9ab0dde367c52227b7fbe8f3349915c4f711a3..0d99d8714d9b4a9c05688329080558d15855af98 100644 (file)
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -70,7 +70,6 @@ system.l2c.mem_side = system.membus.port
 for cpu in cpus:
     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
-    cpu.mem = cpu.dcache
     # connect cpu level-1 caches to shared level-2 cache
     cpu.connectMemPorts(system.toL2Bus)