style: Strip newline when checking lines

[gem5.git] / tests / configs / simple-timing-ruby.py

diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index d3cd7273f9236bb48dbc0edc6e8abf1d2c3d668a..b9fb650e5cf736d2b92c85c432b99d200165033d 100644 (file)
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -28,16 +28,80 @@
 
 import m5
 from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+import os, optparse, sys
 
-import ruby_config
-ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", 1)
+# Get paths we might need
+config_path = os.path.dirname(os.path.abspath(__file__))
+config_root = os.path.dirname(config_path)
+addToPath(config_root+'/configs/common')
+addToPath(config_root+'/configs/ruby')
+addToPath(config_root+'/configs/topologies')
 
+import Ruby
+import Options
+
+parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
+
+# Add the ruby specific and protocol specific options
+Ruby.define_options(parser)
+
+(options, args) = parser.parse_args()
+
+#
+# Set the default cache size and associativity to be very small to encourage
+# races between requests and writebacks.
+#
+options.l1d_size="256B"
+options.l1i_size="256B"
+options.l2_size="512B"
+options.l3_size="1kB"
+options.l1d_assoc=2
+options.l1i_assoc=2
+options.l2_assoc=2
+options.l3_assoc=2
+
+# this is a uniprocessor only test
+options.num_cpus = 1
 cpu = TimingSimpleCPU(cpu_id=0)
-system = System(cpu = cpu,
-                physmem = ruby_memory,
-                membus = Bus())
-system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
-cpu.clock = '2GHz'
-
-root = Root(system = system)
+system = System(cpu = cpu)
+
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+                                   voltage_domain = system.voltage_domain)
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
+                                       voltage_domain = system.voltage_domain)
+
+system.mem_ranges = AddrRange('256MB')
+Ruby.create_system(options, False, system)
+
+# Create a separate clock for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+                                        voltage_domain = system.voltage_domain)
+
+assert(len(system.ruby._cpu_ports) == 1)
+
+# create the interrupt controller
+cpu.createInterruptController()
+
+#
+# Tie the cpu cache ports to the ruby cpu ports and
+# physmem, respectively
+#
+cpu.connectAllPorts(system.ruby._cpu_ports[0])
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root(full_system = False, system = system)
+root.system.mem_mode = 'timing'
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')