tests: Enable test running outside of gem5's source tree

[gem5.git] / tests / configs / simple-timing-ruby.py

diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 4f812f209533f71387ab6194de6703b082d78038..b9fb650e5cf736d2b92c85c432b99d200165033d 100644 (file)
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -35,21 +35,19 @@ import os, optparse, sys
 # Get paths we might need
 config_path = os.path.dirname(os.path.abspath(__file__))
 config_root = os.path.dirname(config_path)
-m5_root = os.path.dirname(config_root)
 addToPath(config_root+'/configs/common')
 addToPath(config_root+'/configs/ruby')
+addToPath(config_root+'/configs/topologies')
 
 import Ruby
+import Options
 
 parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
 
-#
 # Add the ruby specific and protocol specific options
-#
 Ruby.define_options(parser)
 
-execfile(os.path.join(config_root, "configs/common", "Options.py"))
-
 (options, args) = parser.parse_args()
 
 #
@@ -67,19 +65,36 @@ options.l3_assoc=2
 
 # this is a uniprocessor only test
 options.num_cpus = 1
-
 cpu = TimingSimpleCPU(cpu_id=0)
-system = System(cpu = cpu, physmem = PhysicalMemory())
+system = System(cpu = cpu)
+
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+                                   voltage_domain = system.voltage_domain)
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
+                                       voltage_domain = system.voltage_domain)
+
+system.mem_ranges = AddrRange('256MB')
+Ruby.create_system(options, False, system)
+
+# Create a separate clock for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+                                        voltage_domain = system.voltage_domain)
 
-Ruby.create_system(options, system)
+assert(len(system.ruby._cpu_ports) == 1)
 
-assert(len(system.ruby._cpu_ruby_ports) == 1)
+# create the interrupt controller
+cpu.createInterruptController()
 
 #
 # Tie the cpu cache ports to the ruby cpu ports and
 # physmem, respectively
 #
-cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
+cpu.connectAllPorts(system.ruby._cpu_ports[0])
 
 # -----------------------
 # run simulation