tests: Enable test running outside of gem5's source tree

[gem5.git] / tests / configs / simple-timing-ruby.py

diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 94cb15ed45f0b4ac81b33e2dea1f99f5c68bcf7c..b9fb650e5cf736d2b92c85c432b99d200165033d 100644 (file)
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -65,9 +65,9 @@ options.l3_assoc=2
 
 # this is a uniprocessor only test
 options.num_cpus = 1
-
 cpu = TimingSimpleCPU(cpu_id=0)
-system = System(cpu = cpu, physmem = SimpleMemory(null = True))
+system = System(cpu = cpu)
+
 # Dummy voltage domain for all our clock domains
 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
 system.clk_domain = SrcClockDomain(clock = '1GHz',
@@ -79,13 +79,13 @@ system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
                                        voltage_domain = system.voltage_domain)
 
 system.mem_ranges = AddrRange('256MB')
-Ruby.create_system(options, system)
+Ruby.create_system(options, False, system)
 
 # Create a separate clock for Ruby
 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
                                         voltage_domain = system.voltage_domain)
 
-assert(len(system.ruby._cpu_ruby_ports) == 1)
+assert(len(system.ruby._cpu_ports) == 1)
 
 # create the interrupt controller
 cpu.createInterruptController()
@@ -94,7 +94,7 @@ cpu.createInterruptController()
 # Tie the cpu cache ports to the ruby cpu ports and
 # physmem, respectively
 #
-cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
+cpu.connectAllPorts(system.ruby._cpu_ports[0])
 
 # -----------------------
 # run simulation